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AT90USB646 Datasheet(PDF) 408 Page - ATMEL Corporation

Part # AT90USB646
Description  Microcontroller with 64/128K Bytes of ISP Flash and USB Controller
PDF  434 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT90USB646 Datasheet(HTML) 408 Page - ATMEL Corporation

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408
7593A–AVR–02/06
AT90USB64/128
Notes:
1. Values are guidelines only. Actual values are TBD
30.10 External Data Memory Timing
Notes:
1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
VINT2
Internal Voltage Reference
2.56V
2.4
2.56
2.8
V
RREF
Reference Input Resistance
32
k
Ω
RAIN
Analog Input Resistance
100
M
Ω
Table 30-6.
External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state
Symbol
Parameter
8 MHz Oscillator
Variable Oscillator
Unit
Min
Max
Min
Max
01/t
CLCL
Oscillator Frequency
0.0
16
MHz
1t
LHLL
ALE Pulse Width
115
1.0t
CLCL-10
ns
2tAVLL
Address Valid A to ALE Low
57.5
0.5tCLCL-5
(1)
ns
3a
tLLAX_ST
Address Hold After ALE Low,
write access
55
ns
3b
t
LLAX_LD
Address Hold after ALE Low,
read access
55
ns
4t
AVLLC
Address Valid C to ALE Low
57.5
0.5t
CLCL-5
(1)
ns
5tAVRL
Address Valid to RD Low
115
1.0tCLCL-10
ns
6t
AVWL
Address Valid to WR Low
115
1.0t
CLCL-10
ns
7tLLWL
ALE Low to WR Low
47.5
67.5
0.5tCLCL-15
(2)
0.5tCLCL+5
(2)
ns
8tLLRL
ALE Low to RD Low
47.5
67.5
0.5tCLCL-15
(2)
0.5tCLCL+5
(2)
ns
9t
DVRH
Data Setup to RD High
40
40
ns
10
tRLDV
Read Low to Data Valid
75
1.0tCLCL-50
ns
11
tRHDX
Data Hold After RD High
0
0
ns
12
t
RLRH
RD Pulse Width
115
1.0t
CLCL-10
ns
13
tDVWL
Data Setup to WR Low
42.5
0.5tCLCL-20
(1)
ns
14
tWHDX
Data Hold After WR High
115
1.0tCLCL-10
ns
15
t
DVWH
Data Valid to WR High
125
1.0t
CLCL
ns
16
tWLWH
WR Pulse Width
115
1.0tCLCL-10
ns
Table 30-5.
ADC Characteristics (Continued)
Symbol
Parameter
Condition
Min(1)
Typ(1)
Max(1)
Units



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