DS21FF42 datasheet(4/114 Pages) MAXIM

4 / 114 page

DS21FT42/DS21FF42

4 of 114

TABLE OF CONTENTS

FEATURES ................................................................................................................................................1

1. MULTICHIP MODULE (MCM) DESCRIPTION .........................................................................1

2. MCM PIN DESCRIPTION................................................................................................................6

3. DS21FF42 (4 X 4) PCB LAND PATTERN.....................................................................................13

4. DS21FT42 (4 X 3) PCB LAND PATTERN.....................................................................................14

5. DS21Q42 FEATURES ......................................................................................................................15

6. DS21Q42 INTRODUCTION ...........................................................................................................15

7. DS21Q42 PIN FUNCTION DESCRIPTION..................................................................................18

8. DS21Q42 REGISTER MAP.............................................................................................................26

9. PARALLEL PORT...........................................................................................................................30

10.

CONTROL, ID AND TEST REGISTERS..................................................................................30

11.

STATUS AND INFORMATION REGISTERS .........................................................................41

12.

ERROR COUNT REGISTERS....................................................................................................48

13.

DS0 MONITORING FUNCTION ...............................................................................................51

14.

SIGNALING OPERATION .........................................................................................................54

14.1

PROCESSOR BASED SIGNALING..................................................................................................................... 54

14.2

HARDWARE BASED SIGNALING ..................................................................................................................... 56

15.

PER–CHANNEL CODE (IDLE) GENERATION AND LOOPBACK....................................57

15.1

TRANSMIT SIDE CODE GENERATION........................................................................................................... 57

15.1.1

Simple Idle Code Insertion and Per–Channel Loopback................................................................................ 57

15.1.2

Per–Channel Code Insertion............................................................................................................................ 58

15.2

RECEIVE SIDE CODE GENERATION .............................................................................................................. 59

15.2.1

Simple Code Insertion ...................................................................................................................................... 59

15.2.2

Per–Channel Code Insertion............................................................................................................................ 60

16.

CLOCK BLOCKING REGISTERS............................................................................................61

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