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DS21348G Datasheet(PDF) 4 Page - Maxim Integrated Products

Part # DS21348G
Description  3.3V E1/T1/J1 Line Interface
PDF  76 Pages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

DS21348G Datasheet(HTML) 4 Page - Maxim Integrated Products

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DS21348/DS21Q348
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LIST OF FIGURES
Figure 1-1. DS21348 Block Diagram ..........................................................................................................7
Figure 1-2. Receive Logic...........................................................................................................................8
Figure 1-3. Transmit Logic..........................................................................................................................9
Figure 2-1. Parallel Port Mode Pinout (BIS1 = 0, BIS0 = 1 or 0) (TQFP Package) ..................................22
Figure 2-2. Serial Port Mode Pinout (BIS1 = 1, BIS0 = 0) (TQFP Package) ............................................23
Figure 2-3. Hardware Mode Pinout (BIS1 = 1, BIS0 = 1) (TQFP Package) .............................................24
Figure 3-1. Serial Port Operation for Read Access (R = 1) Mode 1 .........................................................27
Figure 3-2. Serial Port Operation for Read Access Mode 2 .....................................................................27
Figure 3-3. Serial Port Operation for Read Access Mode 3 .....................................................................27
Figure 3-4. Serial Port Operation for Read Access Mode 4 .....................................................................28
Figure 3-5. Serial Port Operation for Write Access (R = 0) Modes 1 and 2..............................................28
Figure 3-6. Serial Port Operation for Write Access (R = 0) Modes 3 and 4..............................................28
Figure 7-1. Basic Interface .......................................................................................................................52
Figure 7-2. Protected Interface Using Internal Receive Termination........................................................53
Figure 7-3. Protected Interface Using External Receive Termination.......................................................54
Figure 7-4. E1 Transmit Pulse Template..................................................................................................55
Figure 7-5. T1 Transmit Pulse Template ..................................................................................................56
Figure 7-6. Jitter Tolerance ......................................................................................................................57
Figure 7-7. Jitter Attenuation ....................................................................................................................57
Figure 8-1. 144-CSBGA (17mm x 17mm) Pinout .....................................................................................61
Figure 11-1. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 0) .......................................................65
Figure 11-2. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 0) .......................................................65
Figure 11-3. Motorola Bus Timing (PBTS = 1, BIS1 = 0, BIS0 = 0)..........................................................66
Figure 11-4. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 1) .......................................................68
Figure 11-5. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 1) .......................................................68
Figure 11-6. Motorola Bus Read Timing (PBTS = 1, BIS1 = 0, BIS0 = 1) ................................................69
Figure 11-7. Motorola Bus Write Timing (PBTS = 1, BIS1 = 0, BIS0 = 1) ................................................69
Figure 11-8. Serial Bus Timing (BIS1 = 1, BIS0 = 0) ................................................................................70
Figure 11-9. Receive Side Timing ............................................................................................................71
Figure 11-10. Transmit Side Timing .........................................................................................................72



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