LTC3310 datasheet(11/22 Pages) AD

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LT8644S

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

Low EMI PCB Layout

The LT8644S is specifically designed to minimize EMI

emissions and also to maximize efficiency when switch-

ing at high frequencies. For optimal performance the

LT8644S should use multiple VIN bypass capacitors.

Two small <1µF capacitors can be placed as close as pos-

sible to the LT8644S, one capacitor on each side of the

device (COPT1, COPT2). A third capacitor with a larger value,

22µF or higher, should be placed near COPT1 or COPT2.

See Figure 1 for a recommended PCB layout.

For more detail and PCB design files refer to the Demo

Board guide for the LT8644S.

Note that large, switched currents flow in the LT8644S

PVIN and PGND pins and the input capacitors. The loops

formed by the input capacitors should be as small as pos-

sible by placing the capacitors adjacent to the PVIN and

PGND pins. Capacitors with small case size such as 0402

or 0603 are optimal due to lowest parasitic inductance.

The input capacitors, along with the inductor and out-

put capacitors, should be placed on the same side of the

circuit board, and their connections should be made on

that layer. Place a local, unbroken ground plane under the

application circuit on the layer closest to the surface layer.

The SW and BOOST nodes should be as small as possible.

Finally, keep the FB and RT nodes small so that the ground

traces will shield them from the SW and BOOST nodes.

Figure 1. Recommended PCB Layout for the LT8644S

GROUND VIA

VIN VIA

VOUT VIA

OTHER SIGNAL VIAS

8644S F01

VOUT

COPT2

COPT1

CSS

COUT

CIN3

AGND

TO VOUT & GND

REMOTE SENSE

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