e

EPAD

TM

®

N A

B L

E D

E

GENERAL DESCRIPTION

ALD110800A/ALD110800/ALD110900A/ALD110900 are monolithic

quad/dual N-Channel MOSFETs matched at the factory using ALD’s

proven EPAD® CMOS technology. These devices are intended for low

voltage, small signal applications. The ALD110800/ALD110900 features

zero threshold voltage, which reduces or eliminates input to output

voltage level shift, including circuits where the signal is referenced to

GND or V+. This feature greatly reduces output signal voltage level

shift and enhances signal operating range, especially for very low

operating voltage environments. With these zero threshold devices an

analog circuit with multiple stages can be constructed to operate at

extremely low supply or bias voltage levels. As an example, an input

amplifier stage operating at 0.2V supply voltage has been demonstrated.

ALD110800A/ALD110800/ALD110900A/ALD110900 matched pair

MOSFETs are designed for exceptional device electrical characteris-

tics matching. As these devices are on the same monolithic chip, they

also exhibit excellent tempco tracking characteristics. They are

versatile as design components for a broad range of analog applica-

tions such as basic building blocks for current sources, differential

amplifier input stages, transmission gates, and multiplexer applications.

Besides matched pair electrical characteristics, each individual

MOSFET also exhibits well controlled parameters, enabling the user

to depend on tight design limits. Even units from different batches

and different date of manufacture have correspondingly well matched

characteristics.

These devices are built for minimum offset voltage and differential

thermal response, and they are designed for switching and amplifying

applications in +0.2V to +10V systems where low input bias current,

of these devices are set at +0.0V, which classify them as both enhance-

ment mode and depletion mode devices. When the gate is set at 0.0V,

with output voltage level biased at or near input voltage level without

voltage level shift. These devices exhibit same well controlled turn-off

and sub-threshold characteristics as standard enhancement mode

MOSFETs.

The ALD110800A/ALD110800/ALD110900A/ALD110900 are MOSFET

devices that feature high input impedance (10

gain (>10

current of 3mA and input leakage current of 30pA at 25°C is = 3mA/

30pA = 100,000,000. For most applications, connect V+ pin to the most

positive voltage potential (or left open unused) and V- and N/C pins to

the most negative voltage potential in the system. All other pins must

have voltages within these voltage limits.

MATCHED PAIR MOSFET ARRAY

N/C*

1

2

3

14

15

16

4

13

5

12

N/C*

6

7

8

10

11

N/C*

N/C*

9

ALD110800

M 4

M 3

M 1

M 2

V-

N/C*

ALD110900

1

2

3

6

7

8

4

5

M 1

M 2

V-

N/C*

V-

V-

FEATURES

• Precision zero threshold voltage mode

• Matched MOSFET to MOSFET characteristics

• Tight lot to lot parametric control

• Low input capacitance

• Low input/output leakage currents

APPLICATIONS

• Very low voltage analog and digital circuits

• Zero power fail safe circuits

• Backup battery circuits & power failure detector

• Low level voltage clamp & zero crossing detector

• Source followers and buffers

• Precision current mirrors and current sources

• Capacitives probes and sensor interfaces

• Charge detectors and charge integrators

• Differential amplifier input stage

• High side switches

• Peak detectors and level shifters

• Sample and Hold

• Current multipliers

• Analog switches / multiplexers

• Voltage comparators and level shifters

ALD110800/ALD110800A/ALD110900/ALD110900A

ORDERING INFORMATION

* Contact factory for industrial temp. range or user-specified threshold voltage values

Operating Temperature Range*

0°C to +70°C0°C to +70°C

16-Pin

16-Pin

8-Pin

8-Pin

Plastic Dip

SOIC

Plastic Dip

SOIC

Package

Package

Package

Package

ALD110800APC

ALD110800ASC ALD110900APA ALD110900ASA

ALD110800PC

ALD110800SC

ALD110900PA

ALD110900SA

PC, SC PACKAGES

PA, SA PACKAGES

PIN CONFIGURATION

Rev 1.0-0506 ©2005 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, California 94089-1706 Tel: (408) 747-1155 Fax: (408) 747-1286

www.aldinc.com

*N/C pins are internally connected.

Connect to V- to reduce noise