Note 3: The MAX1464_ is operational from 3.0V to 5.5V. However, in order for the valid Apple resistor-divider network to function,

Note 4: Guaranteed by design, not production tested.

Note 5: Guaranteed by design.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

0.25

0.4

V

0.8

2.0

V

50

150

F

A

LOGIC INPUTS (CB0, CB1, SDA, SCL)

Input Logic High Voltage

1.4

V

Input Logic Low Voltage

0.4

V

Input Leakage Current

-1

+1

F

A

CB0/CB1 Debounce Time

250

F

s

OPEN-DRAIN LOGIC OUTPUTS (SDA, INT, CEN, CEN)

INT, SDA, CEN Output Low

Voltage

0.4

V

INT, SDA, CEN Output Leakage

Current

1

F

A

CEN, INT, Output High Voltage

V

CEN, INT, Output Leakage Current

1

F

A

Q

10

%

400

kHz

Bus Free Time Between STOP

and START Conditions

1.3

F

s

START Condition Setup Time

0.6

F

s

Repeated START Condition

Setup Time

70% of SCL to 70% of SDA

0.6

F

s

START Condition Hold Time

30% of SDA to 70% of SCL

0.6

F

s

STOP Condition Setup Time

70% of SCL to 30% of SDA

0.6

F

s

Clock Low Period

30% to 30%

1.3

F

s

Clock High Period

70% to 70%

0.6

F

s

Data Valid to SCL Rise Time

Write setup time

100

ns

Data Hold Time to SCL Fall

Write hold time

100

ns

PROTECTION SPECIFICATIONS

ESD Protection

Human Body Model

DP and DM pins

Q

15

kV

All other pins

Q

2

Electrical Characteristics (continued)

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MAX14640–MAX14644/MAX14651

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