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DS34S102 Datasheet(PDF) 4 Page - Maxim Integrated Products

Part # DS34S102
Description  DS34S101, DS34S102, DS34S104, DS34S108 Single/Dual/Quad/Octal TDM-over-Packet Chip
PDF  198 Pages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

DS34S102 Datasheet(HTML) 4 Page - Maxim Integrated Products

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____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609
4 of 198
List of Figures
Figure 5-1. TDMoP in a Metropolitan Packet Switched Network ........................................................................... 12
Figure 5-2. TDMoP in Cellular Backhaul............................................................................................................... 13
Figure 6-1. Top-Level Block Diagram ................................................................................................................... 14
Figure 10-1. CPU Interface Functional Diagram .................................................................................................. 28
Figure 10-2. Write Access, 32-Bit Bus................................................................................................................. 29
Figure 10-3. Read Access, 32-Bit Bus................................................................................................................. 30
Figure 10-4. Read/Write Access, 16-Bit Bus........................................................................................................ 30
Figure 10-5. Write Access to the SDRAM, 16-Bit Bus.......................................................................................... 31
Figure 10-6. Read Access to the SDRAM, 16-Bit Bus.......................................................................................... 31
Figure 10-7. SPI Interface with One Slave........................................................................................................... 32
Figure 10-8. SPI Interface Timing, SPI_CP=0 ..................................................................................................... 32
Figure 10-9. SPI Interface Timing, SPI_CP=1 ..................................................................................................... 32
Figure 10-10. TDM-over-Packet Encapsulation Formats...................................................................................... 38
Figure 10-11. Single VLAN Tag Format............................................................................................................... 39
Figure 10-12. Stacked VLAN Tag Format............................................................................................................ 39
Figure 10-13. UDP/IPv4 Header Format.............................................................................................................. 39
Figure 10-14. UDP/IPv6 Header Format.............................................................................................................. 40
Figure 10-15. MPLS Header Format ................................................................................................................... 41
Figure 10-16. MEF Header Format...................................................................................................................... 41
Figure 10-17. L2TPv3/IPv4 Header Format......................................................................................................... 42
Figure 10-18. L2TPv3/IPv6 Header Format......................................................................................................... 43
Figure 10-19. Control Word Format..................................................................................................................... 43
Figure 10-20. RTP Header Format...................................................................................................................... 44
Figure 10-21. VCCV OAM Packet Format ........................................................................................................... 45
Figure 10-22. UDP/IP-Specific OAM Packet Format............................................................................................ 46
Figure 10-23. TDM Connectivity over a PSN....................................................................................................... 47
Figure 10-24. TDMoP Packet Format in a Typical Application ............................................................................. 47
Figure 10-25. TDMoMPLS Packet Format in a Typical Application ...................................................................... 48
Figure 10-26. CAS Transmitted in the TDM-to-Ethernet Direction........................................................................ 50
Figure 10-27. Transmit SW CAS Table Format for E1 and T1-ESF Interfaces ..................................................... 51
Figure 10-28. Transmit SW CAS Table Format for T1-SF Interfaces.................................................................... 51
Figure 10-29. E1 MF Interface RSIG Timing Diagram (two_clocks=1) ................................................................. 51
Figure 10-30. T1 ESF Interface RSIG Timing Diagram (two_clocks=0)................................................................ 52
Figure 10-31. T1 SF Interface RSIG (two_clocks=0) – Timing Diagram ............................................................... 52
Figure 10-32. CAS Transmitted in the Ethernet-to-TDM Direction........................................................................ 53
Figure 10-33. E1 MF Interface TSIG Timing Diagram.......................................................................................... 54
Figure 10-34. T1 ESF Interface TSIG Timing Diagram ........................................................................................ 54
Figure 10-35. T1 SF Interface TSIG Timing Diagram........................................................................................... 54
Figure 10-36. AAL1 Mapping, General ................................................................................................................ 55
Figure 10-37. AAL1 Mapping, Structured-Without-CAS Bundles.......................................................................... 56
Figure 10-38. HDLC Mapping ............................................................................................................................. 57
Figure 10-39. SAToP Unstructured Packet Mapping............................................................................................ 58
Figure 10-40. CESoPSN Structured-Without-CAS Mapping................................................................................. 59
Figure 10-41. CESoPSN Structured-With-CAS Mapping (No Frag, E1 Example)................................................. 59
Figure 10-42. CESoPSN Structured-With-CAS Mapping (No Frag, T1-ESF Example) ......................................... 60
Figure 10-43. CESoPSN Structured-With-CAS Mapping (No Frag, T1-SF Example) ........................................... 60
Figure 10-44. CESoPSN Structured-With-CAS Mapping (Frag, E1 Example) ...................................................... 61
Figure 10-45. SDRAM Access through the SDRAM Controller............................................................................. 63
Figure 10-46. Loop Timing in TDM Networks....................................................................................................... 63
Figure 10-47. Timing in TDM-over-Packet........................................................................................................... 64
Figure 10-48. Jitter Buffer Parameters................................................................................................................. 65
Figure 10-49. TDM-over-Packet Data Flow Diagram ........................................................................................... 67
Figure 10-50. Free Buffer Pool Operation............................................................................................................ 71
Figure 10-51. TDM-to-Ethernet Flow................................................................................................................... 72
Figure 10-52. Ethernet-to-TDM Flow ................................................................................................................... 73



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