INF8574

2

PINNING

SYMBOL

PIN

DESCRIPTION

A0

1

address input 0

A1

2

address input 1

A2

3

address input 2

P0

4

quasi-bidirectional I/O Port 0

P1

5

quasi-bidirectional I/O Port 1

P2

6

quasi-bidirectional I/O Port 2

P3

7

quasi-bidirectional I/O Port 3

8

supply ground

P4

9

quasi-bidirectional I/O Port 4

P5

10

quasi-bidirectional I/O Port 5

P6

11

quasi-bidirectional I/O Port 6

P7

12

quasi-bidirectional I/O Port 7

INT

13

interrupt output (active LOW)

SCL

14

serial clock line

SDA

15

serial data line

16

supply voltage

are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a posi-

tive supply via a pull-up resistor when connected to the output stages of a device. Data transfer

may be initiated only when the bus is not busy.

Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable

during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted

as control signals

Bit transfer.

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the

data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of

the data line while the clock is HIGH is defined as the stop condition (P).

Definition of start and stop conditions.