5 Pin Configuration and Functions

A

B

C

D

E

F

G

H

1

2

3

4

5

6

Figure 5-1. YVA Package 48-Pin DSBGA Top View

Table 5-1. Pin Functions

PIN

TYPE(1)

DESCRIPTION

NAME

NO.

GND

A1

G

Ground

GND

A2

G

Ground

OE/ RESET

A3

I/O

Output Enable/ RESET (Open-Drain I/O). When Low, this input holds the address

counter reset and the DATA and CLKOUT outputs are placed in a high-impedance state.

This is a bidirectional open-drain pin that is held Low while the PROM completes the

internal power-on reset sequence. Polarity is not programmable. Pin must be pulled

DNC

A4

—

Do Not Connect. Leave unconnected.

D6

A5

—

Do Not Connect. Leave unconnected.

D7

A6

—

Do Not Connect. Leave unconnected.

VCCINT1

B1

P

Positive 1.8-V supply voltage for internal logic.

VCCO1

B2

P

Positive supply voltage connected to the output voltage drivers and internal buffers.

CLK

B3

I

Do Not Connect. Leave unconnected.

CE

B4

I

Chip Enable Input. When CE is High, the device is put into low-power standby mode,

the address counter is reset, and the DATA and CLKOUT outputs are placed in a high

D5

B5

—

Do Not Connect. Leave unconnected.

GND

B6

G

Ground

BUSY

C1

—

Do Not Connect. Leave unconnected.

CLKOUT

C2

—

Configuration clock output. Each rising edge on the CLK input increments the internal

address counter. Pin must be pulled High and Low using an external 100-Ω pull-up

DNC

C3

—

Do Not Connect. Leave unconnected.

DNC

C4

—

Do Not Connect. Leave unconnected.

D4

C5

—

Do Not Connect. Leave unconnected.

DLPR410

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

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