ADP5071 datasheet(3/17 Pages) AD

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Data Sheet

ADP5073

Rev. A | Page 3 of 17

SPECIFICATIONS

PVIN = AVIN = 2.85 V to 15 V, VOUT = −15 V, fSW = 1200 kHz, TJ = −40°C to +125°C for minimum/maximum specifications, and

TA = 25°C for typical specifications, unless otherwise noted.

Table 2.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

INPUT SUPPLY VOLTAGE RANGE

VIN

2.85

PVIN, AVIN

QUIESCENT CURRENT

Operating Quiescent Current

PVIN, AVIN (Total)

1.8

4.0

No switching, EN = high, PVIN = AVIN =

5 V

Shutdown Current

ISHDN

µA

No switching, EN = low, PVIN = AVIN =

5 V, −40°C ≤ TJ ≤ +85°C

UVLO

System UVLO Threshold

AVIN

Rising

VUVLO_RISING

2.8

2.85

Falling

VUVLO_FALLING

2.5

2.55

Hysteresis

VHYS

0.25

OSCILLATOR CIRCUIT

Switching Frequency

fSW

1.130

1.200

1.270

MHz

SYNC/FREQ = low

2.240

2.400

2.560

MHz

SYNC/FREQ = high (connect to VREG)

SYNC/FREQ Input

Input Clock Range

fSYNC

1.000

2.600

MHz

Input Clock Minimum On Pulse Width

tSYNC_MIN_ON

100

Input Clock Minimum Off Pulse Width

tSYNC_MIN_OFF

100

Input Clock High Logic

VH (SYNC)

1.3

Input Clock Low Logic

VL (SYNC)

0.4

PRECISION ENABLING (EN)

High Level Threshold

VTH_H

1.125

1.15

1.175

Low Level Threshold

VTH_L

1.025

1.05

1.075

Shutdown Mode

VTH_S

0.4

Internal circuitry disabled to achieve ISHDN

Pull-Down Resistance

REN

1.48

MΩ

INTERNAL REGULATOR

VREG Output Voltage

VREG

4.25

INVERTING REGULATOR

Reference Voltage

VREF

1.60

Accuracy

−0.5

+0.5

TJ = 25°C

−1.5

+1.5

TJ = −40°C to +125°C

Feedback Voltage

VREF − VFB

0.8

Accuracy

−0.5

+0.5

TJ = 25°C

−1.5

+1.5

TJ = −40°C to +125°C

Feedback Bias Current

IFB

0.1

µA

Overvoltage Protection Threshold

VOV

0.74

At the FB pin after soft start is complete

Power-Good Threshold

VPG (GOOD)

0.7

VREF − VFB ≥ VPG (GOOD)

VPG (BAD)

0.68

VREF − VFB ≤ VPG (BAD)

Power-Good FET On Resistance

RDS_PG (ON)

Ω

Power-Good FET Maximum Drain Source

Voltage

VDS_PG(MAX)

5.5

Power-Good Supply Voltage

VPG(SUPPLY)

1.4

Voltage required on PVIN pin for power-

good FET to pull down

Load Regulation

∆(VREF − VFB)/

∆ILOAD

0.0025

%/A

ILOAD = 100 mA to 500 mA (regulator

not in skip mode)

Line Regulation

∆(VREF − VFB)/

∆VIN

0.02

%/V

VIN = 2.85 V to 14.5 V, ILOAD = 15 mA

(regulator not in skip mode_

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