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AF1333PU Datasheet(PDF) 2 Page - Anachip Corp |
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AF1333PU Datasheet(HTML) 2 Page - Anachip Corp |
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2 / 5 page ![]() AF1333P P-Channel Enhancement Mode Power MOSFET Anachip Corp. www.anachip.com.tw Rev. 1.0 Oct 15, 2004 2/5 Absolute Maximum Ratings Symbol Parameter Rating Unit VDS Drain-Source Voltage -20 V VGS Gate-Source Voltage ±12 V TA=25ºC -550 ID Continuous Drain Current (Note 1) TA=70ºC -440 mA IDM Pulsed Drain Current (Note 2, 3) -2.5 A Total Power Dissipation TA=25ºC 0.35 W PD Linear Derating Factor 0.003 W/ oC TSTG Storage Temperature Range -55 to +150 oC TJ Operating Junction Temperature Range -55 to +150 oC Thermal Data Symbol Parameter Value Unit Rthj-a Thermal Resistance Junction-Ambient (Note 1) Max. 360 ºC/W Electrical Characteristics at T A=25 oC (unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Unit BVDSS Drain-Source Breakdown Voltage VGS=0V, ID=-250uA -20 - - V ∆BVDSS / ∆TJ Breakdown Voltage Temperature Coefficient Reference to 25 oC, ID=-1mA - 0.01 - V/ oC VGS=-10V, ID=-550mA - - 600 VGS=-4.5V, ID=-550mA - - 800 RDS(ON) Static Drain-Source On-Resistance VGS=-2.5V, ID=-300mA - - 1000 mΩ VGS(th) Gate Threshold Voltage VDS=VGS, ID=-250uA -0.5 - -1.2 V gfs Forward Transconductance VDS=-5V, ID=-500mA - 1 - S Drain-Source Leakage Current (TJ=25 oC) VDS=-20V, VGS=0V - - -1 IDSS Drain-Source Leakage Current (TJ=70 oC) VDS=-16V, VGS=0V - - -10 uA IGSS Gate-Source Leakage VGS=±12V - - ±100 nA Qg Total Gate Charge (Note 3) - 1.7 2.7 Qgs Gate-Source Charge - 0.3 - Qgd Gate-Drain (“Miller”) Charge ID=-500mA, VDS=-16V, VGS=-4.5V - 0.4 - nC td(on) Turn-On Delay Time (Note 3) - 5 - tr Rise Time - 8 - td(off) Turn-Off Delay Time - 10 - tf Fall-Time VDS=-10V, ID=-500mA, RG=3.3Ω, VGS=-5V RD=20Ω - 2 - ns Ciss Input Capacitance - 66 105.6 Coss Output Capacitance - 25 - Crss Reverse Transfer Capacitance VGS=0V, VDS=-10V, f=1.0MHz - 20 - pF Source-Drain Diode Symbol Parameter Test Conditions Min. Typ. Max. Unit VDS Forward On Voltage (Note 3) IS=-300mA, VGS=0V - - -1.2 V Note 1: Surface mounted on FR4 board, t ≤ 10 sec. Note 2: Pulse width limited by Max. junction temperature. Note 3: Pulse width ≤ 300us, duty cycle ≤ 2%. |
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