TMUX7212 datasheet(32/48 Pages) TI

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11 Power Supply Recommendations

The TMUX7212-Q1 device operates across a wide supply range of ±4.5 V to ±22 V (4.5 V to 44 V in single-

supply mode). The device also perform well with asymmetrical supplies such as VDD = 12 V and VSS = –5 V.

Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply

rails to other components. Good power-supply decoupling is important to achieve optimum performance. For

improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF at both the VDD

and VSS pins to ground. Place the bypass capacitors as close to the power supply pins of the device as possible

using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that

offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling

purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias

for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple vias

in parallel lowers the overall inductance and is beneficial for connections to ground and power planes. Always

ensure the ground (GND) connection is established before supplies are ramped.

12 Layout

12.1 Layout Guidelines

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of

the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This

increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance

of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must

turn corners. Figure 12-1 shows progressively better techniques of rounding corners. Only the last example

(BEST) maintains constant trace width and minimizes reflections.

WORST

BETTER

BEST

1W min.

Figure 12-1. Trace Example

Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance

changes. When a via must be used, increase the clearance size around it to minimize its capacitance.

Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up

interference from the other layers of the board. Be careful when designing test points, through-hole pins are not

recommended at high frequencies.

Some key considerations are:

• For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD/VSS and

GND. We recommend a 0.1 µF and 1 µF capacitor, placing the lowest value capacitor as close to the pin as

possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.

• Keep the input lines as short as possible.

• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.

• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

• Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground

planes.

TMUX7212-Q1

SCDS439 – SEPTEMBER 2021

www.ti.com

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