8.3.2.2 Powered-Off Protection

(Sx) pins of the device remain in the high impedance (Hi-Z) state, and the device performance remains within

the leakage performance mentioned in the Electrical Specifications. Powered-off protection minimizes system

complexity by removing the need to control power supply sequencing of the system. The feature prevents errant

voltages on the input source pins from reaching the rest of the system and maintains isolation when the system

is powering up. Without powered-off protection, signal on the input source pins can back-power the supply rails

through internal ESD diodes and cause potential damage to the system.

must always be present to ensure proper operation. Source and drain voltage levels of up to ±60 V are blocked

in the powered-off condition.

8.3.2.3 Fail-Safe Logic

Fail-safe logic circuitry allows voltages on the digital control pins to be applied before the supply pins, protecting

the device from potential damage. The switch is specified to be in the OFF state, regardless of the state of the

digital logic signals. The digital inputs are protected against positive faults of up to +44 V in the powered-off

condition, but do not offer protection against the negative overvoltage condition.

8.3.2.4 Overvoltage Protection and Detection

The TMUX7308F and TMUX7309F detect overvoltage inputs by comparing the voltage on a source pin (Sx) with

When an overvoltage is detected, the switch automatically turns OFF regardless of the digital logic controls. The

source pin becomes high impedance and ensures only small leakage current flows through the switch. When

the fault channel is selected by the digital logic control, the drain pin (D or Dx) is pulled to the supply that was

result, the drain current is limited to roughly 1 mA during a shorted load (to GND) condition. Figure depicts the

protection structure of the device.

8.3.2.5 Latch-Up Immunity

Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition

is caused by a trigger (current injection or overvoltage); but once activated, the low impedance path remains

even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic

damage due to the excessive current levels. The latch-up condition typically requires a power cycle to eliminate

the low impedance path.

In the TMUX7308F and TMUX7309F devices, an insulating oxide layer is placed on top of the silicon substrate

to prevent any parasitic junctions from forming. As a result, the devices are latch-up immune under all

circumstances by device construction.

8.3.2.6 EMC Protection

The TMUX7308F and TMUX7309F are not intended for standalone electromagnetic compatibility (EMC)

protection in industrial applications. There are three common high voltage transient specifications that govern

industrial high voltage transient specification: IEC61000-4-2 (ESD), IEC61000-4-4 (EFT), and IEC61000-4-5

(surge immunity). A transient voltage suppressor (TVS), along with some low-value series current limiting

resistor, are required to prevent source input voltages from going above the rated ±60 V limits.

When selecting a TVS protection device, it is critical to ensure that the maximum working voltage is greater than

both the normal operating range of the input source pins to be protected and any known system common-mode

overvoltage that may be present due to incorrect wiring, loss of power, or short circuit. Figure 8-1 shows one

example of the proper design window when selecting a TVS device.

TMUX7308F

SCDS403A – FEBRUARY 2021 – REVISED OCTOBER 2021

www.ti.com

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