54AC240 datasheet(5/6 Pages) SS

5 / 6 page

Advanced CMOS Logic – 54AC240

Rev 1.1

30/11/21

AC Electrical Characteristics8 (V

CC 3.3V ±0.3V, VCC 5V ±0.3V)

LIMITS

PARAMETER

8. Not production tested in die form, characterized by chip design

9. Used to determine the no-load dynamic power consumption: PD = CPD VCC

2f + ICC VCC.

SYMBOL

VCC

CONDITIONS

UNITS

FULL RANGE

25°C

85°C

3.3V

8.0

9.0

11.0

CL = 50pF,

tPLH,

5.0V

Input

tr = tf = 3ns

6.5

7.0

8.5

3.3V

8.0

8.5

10.5

Maximum

Propagation Delay

Input A to Output Y

CL = 50pF,

(Figure 1,3)

tPHL

5.0V

Input

tr = tf = 3ns

6.0

6.5

8.0

3.3V

10.5

11.0

11.5

CL = 50pF,

tPZH,

5.0V

Input

tr = tf = 3ns

7.0

8.0

9.0

3.3V

10.0

11.0

13.0

Output Enable Time

OE to 1Y or 2Y

(Figure 2,4)

tPZL

5.0V

CL = 50pF,

Input

tr = tf = 3ns

8.0

8.5

10.5

3.3V

10.5

12.5

tPHZ

5.0V

CL = 50pF,

Input

tr = tf = 3ns

9.0

9.5

10.5

3.3V

10.5

11.5

13.5

Output Enable Time

OE to 1Y or 2Y

CL = 50pF,

(Figure 2,4)

tPLZ

5.0V

Input

tr = tf = 3ns

9.0

9.5

11.0

Maximum Input

Capacitance

CIN

4.5

TYPICAL

Power Dissipation

TJ = 25°C,

Capacitance

CPD

VCC = 5.0V

Page 5 of 6

54AC240 Datasheet(PDF) 5 Page - Silicon Supplies

54AC240 Datasheet(HTML) 5 Page - Silicon Supplies

Html Pages

1 2 3 4 5 6

Datasheet Download

Link URL