MIC5021 datasheet(10/24 Pages) MICROCHIP

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MIC5021

DS20005677B-page 10

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2016 - 2021 Microchip Technology Inc. and its subsidiaries.

5.0

FUNCTIONAL DESCRIPTION

Refer to the MIC5021 .

5.1

Input

A signal greater than 1.4V (nominal) applied to the

MIC5021 INPUT causes gate enhancement on an

external MOSFET turning the MOSFET on.

An internal pull-down resistor ensures that an open

input remains low, keeping the external MOSFET

turned off.

5.2

Gate Output

Rapid rise and fall times on the gate output are possible

because each input state change triggers a one-shot

which activates a high-value current sink (10I2) for a

short time. This draws a high current though a current

mirror circuit causing the output transistors to quickly

charge or discharge the external MOSFET’s gate.

A second current sink continuously draws the lower

value of current used to maintain the gate voltage for

the selected state.

An internal charge pump utilizes an external “boost”

capacitor connected between VBOOST and the source

of the external MOSFET (Refer to the Typical Applica-

tion Circuit). The boost capacitor stores charge when

the MOSFET is off. As the MOSFET turns on, its

source to ground voltage increases and is added to the

voltage across the capacitor, raising the VBOOST pin

voltage. The boost capacitor charge is directed through

the gate pin to quickly charge the MOSFET’s gate to

16V maximum above VDD. The internal charge pump

maintains the gate voltage.

An internal Zener diode protects the external MOSFET

by limiting the gate to source voltage.

5.3

SENSE Inputs

The MIC5021’s 50 mV (nominal) trip voltage is created

by internal current sources that force approximately

5 µA out of SENSE+ and approximately 15 µA (at trip)

out of SENSE–. When SENSE– is 50mV or more below

SENSE+, SENSE– steals base current from an internal

drive transistor shutting off the external MOSFET.

5.4

Overcurrent Limiting

Current source I1 charges CINT upon power up. An

optional external capacitor connected to CT is kept dis-

charged through a MOSFET Q1.

A fault condition (>50 mV from SENSE+ to SENSE–)

causes the overcurrent comparator to enable current

sink 2I1 which overcomes current source I1 to dis-

charge CINT in a short time. When CINT is discharged,

the input is disabled, which turns off the gate output,

and CINT and CT are ready to be charged.

When the gate output turns the MOSFET off, the over-

current signal is removed from the sense inputs which

deactivates current sink 2I1.This allows CINT and the

optional capacitor connected to CT to recharge. A

Schmitt trigger delays the retry while the capacitor(s)

recharge. Retry delay is increased by connecting a

capacitor to CT (optional).

The retry cycle will continue until the fault is removed or

the input is changed to TTL low.

If CT is connected to ground, the circuit will not retry

upon a fault condition.

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