LTC4089 datasheet(9/26 Pages) AD

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LTC4041

Rev A

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PIN FUNCTIONS

VSYS (Pins 1, 24): System Voltage Output Pin. This pin is

used to provide power to an external load from either the

primary input supply or from the backup supercapacitor

if the primary input supply is not available. In addition to

supplying power to the load, this pin provides power to

charge the supercapacitor when input power is available.

VSYS should be bypassed with a low ESR ceramic capaci-

tor of at least 100μF to GND.

PROG (Pin 2): Charge Current Program Pin. An external

resistor from the PROG pin to GND programs the full-

scale charge current. At full scale, the PROG pin servos

to 0.8V. The ratio of the SCAP pin current to the PROG

pin current is internally set to 2500.

IMON (Pin 3): VSYS Current Monitoring Pin. The ratio

between the IMON pin voltage and the differential voltage

between VIN and CLN is internally set to 32. Charge cur-

rent is reduced when the IMON pin voltage reaches 0.8V.

CHGEN (Pin 4): Disable Pin for the Supercapacitor

Charger. Tie this pin to GND to enable the charger or to

a voltage above 1.2V to disable it. Do not leave this pin

unconnected.

BSTEN (Pin 5): Disable Pin for the Backup Boost Converter.

Tie this pin to GND to enable the boost backup or to a volt-

age above 1.2V to disable backup. Do not leave this pin

unconnected.

VIN (Pin 6): Input Pin. Power can be applied directly to

this pin if the optional overvoltage protection (OVP) fea-

ture is not used. For applications where the OVP feature

is required, connect an external N-channel FET between

the input supply VPWR and this pin.

CLN (Pin 7): Negative terminal pin for an external cur-

rent limit sense resistor connected between VIN and this

pin. This resistor is used to monitor the current from VIN

to VSYS. The LTC4041 reduces charge current in order

to maintain 25mV across this sense resistor. However,

it does not limit the system current if the drop exceeds

25mV.

CAPFLT (Pin 8): Open-Drain Supercapacitor Fault Status

Output. In charger mode, if the voltage of any single

supercapacitor exceeds 2.7V, this pin is pulled low and

charging is disabled. In backup mode, if the voltage of any

single supercapacitor falls below –20mV, the CAPFLT pin

is pulled low and the backup boost is disabled. To keep

charging or backup enabled under any supercapacitor

fault condition, tie this pin high. The current pull-down

capability of the CAPFLT is 10µA.

BAL (Pin 9): Supercapacitor Balance Point. Connect the

common node of a stack of two supercapacitors to this

pin. An internal supercapacitor balancer drives this node

to a voltage that is half of VSCAP. Leave this pin open if

only one supercapacitor is used.

RSTFB (Pin 10): SYSGD Comparator Input. High imped-

ance input to an accurate comparator with a 0.74V falling

threshold and 20mV hysteresis. This pin controls the state

of the SYSGD output pin. An external resistor divider is

used between VSYS, RSTFB and GND. It can be the same

resistor divider as the BSTFB divider to monitor the sys-

tem output voltage VSYS. See the Applications Information

section.

SYSGD (Pin 11): Open-Drain Status Output of the SYSGD

Comparator. This pin is pulled to GND by an internal

N-channel MOSFET whenever the RSTFB pin falls below

0.74V.

CAPFB (Pin 12): Supercapacitor (Single or a Stack of

Two) Feedback Pin. An external divider between the

SCAP pin and GND with the center tap connected to the

CAPFB pin programs the final supercapacitor (or stack)

voltage(VCHG). The voltage on this pin nominally servos

to 0.8V.

CAPGD (Pin 13): Supercapacitor Power Good Indicator

Pin. The open-drain output is pulled low until CAPFB rises

to 92.5% of its regulation point.

PFO (Pin 14): Open-Drain Power-Fail Status Output. This

pin is pulled to GND by an internal N-channel MOSFET

when the PFI input is below the falling threshold of the

power-fail comparator. Once the PFI input rises above the

rising threshold, this pin becomes high impedance.

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