3D3444 datasheet(2/6 Pages) DATADELAY

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3D3444

APPLICATION NOTES

line to its normal operation. The device contains

an SO output, which can be used to cascade

multiple devices, as shown in Figure 3.

THEORY OF OPERATION

The quad 4-bit programmable 3D3444 delay line

architecture is comprised of a number of delay

cells connected in series with their respective

outputs multiplexed onto the Delay Out pin (O1-

O4) by the user-selected programming data.

Each delay cell produces at its output a replica of

the signal present at its input, shifted in time.

Each of the four lines can be controlled

independently, via the serial interface.

TABLE 2: BIT SEQUENCE

Bit

Delay

Line

Function

Output Enable

Address Bit 3

Address Bit 2

Address Bit 1

Address Bit 0

Address Bit 3

Address Bit 2

Address Bit 1

Address Bit 0

Address Bit 3

Address Bit 2

Address Bit 1

Address Bit 0

Address Bit 3

Address Bit 2

Address Bit 1

Address Bit 0

PROGRAMMED DELAY (ADDRESS)

INTERFACE

Figure 1 illustrates the main functional blocks of

the 3D3444 device. Since the device is a CMOS

design, all unused input pins must be returned to

well defined logic levels (VDD or GND). The

delays are adjusted by first shifting a 20-bit

programming word into the device via the SC and

SI pins, then strobing the AL signal to latch the

values. The bit sequence is shown in Table 2,

and the associated timing diagram is shown in

Figure 2. Each line has associated with it an

enable bit. Setting this bit low will force the

corresponding delay line output to a high

impedance state, while setting it high returns the

DELAY

LINE

20-BIT LATCH

20-BIT SHIFT REGISTER

Figure 1: Functional block diagram

DELAY

LINE

DELAY

LINE

DELAY

LINE

ENABLES

ADDR4

ADDR3

ADDR2

ADDR1

Doc #00119

DATA DELAY DEVICES, INC.

8/2/02

Tel: 973-773-2299

Fax: 973-773-9672

http://www.datadelay.com

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