12 Layout

12.1 Layout Guidelines

Figure 12-1 illustrates an example of a PCB layout for a data acquisition system using the REF70. Some key

considerations are:

• Connect low-ESR, 1-uF to 100-uF capacitor at OUTF of the REF70.

• Decouple other active devices in the system per the device specifications.

• Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise

pickup.

• Place the external components as close to the device as possible. This configuration prevents parasitic errors

(such as the Seebeck effect) from occurring.

• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when absolutely necessary.

12.2 Layout Example

Copyright © 2020, Texas Instruments Incorporated

GND

VIN

EN

GND

GND

OUTF

OUTS

GND

1

2

3

4

8

7

6

5

Analog GND

Input Voltage

VREF

Enable Control

Figure 12-1. Layout Example

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REF70

SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021

Copyright © 2021 Texas Instruments Incorporated

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