USB7252TSLASHKDX datasheet(61/65 Pages) MICROCHIP

61 / 65 page

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2018 - 2020 Microchip Technology Inc.

DS00002736D-page 61

USB7252

Figure 2-1

Updated internal PHY numbering to match

physical port numbering detailed in new

Section 3.4, Physical and Logical Port Map-

ping

Table 3-5, Table 3-6

Updated programmable function pin assign-

ment names from “DP3_DISCHARGE”,

“DP3_VCONN1”, and “DP3_VCONN2” to

“DP2_DISCHARGE”, “DP2_VCONN1”, and

“DP2_VCONN2”, respectively.

Section 9.6.1, Power Supply and

RESET_N Sequence Timing

Clarified section and added links to the rise

time information in Section 9.2, Operating

Conditions**.

Section 9.7.2, External Reference

Clock (CLK_IN)

Clarified first sentence.

Section 9.6.9, I2S Timing

Corrected hyperlink.

DS00002736B (05-15-19)

Cover

Corrected RAM to 96kB.

Section 2.1, General Description

Updated description to clearly indicate num-

ber of USB 3.1 and USB 2.0 ports.

Section 2.1, General Description

Added note detailing logical vs. physical port

numbering.

Table 3-1

• Updated TEST1/TEST2/TEST3 descrip-

tions to indicate they must be pulled-up to

3.3V via a 10 k resistor.

• Updated ATEST description to indicate it

must be left unconnected.

Section 3.3.4, PF[31:2] Configuration

(CFG_STRAP[2:1])

Updated note to indicate CFG_STRAP3 must

be pulled-down to ground via a 200 k resis-

tor.

Section 3.3.4, PF[31:2] Configuration

(CFG_STRAP[2:1])

Corrected PRT_CTLx port number assign-

ments.

Section 9.2, Operating Conditions**

Updated VDD11 operational supply voltage

minimum to 1.09V.

DS00002736A (08-14-18)

All

Initial Release

TABLE A-1:

REVISION HISTORY (CONTINUED)

Revision Level & Date

Section/Figure/Entry

Correction

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