MAX11152 datasheet(21/27 Pages) MAXIM

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MAX11152

18-Bit, 500ksps, +5V Unipolar Input, SAR ADC,

in Tiny 10-Pin µMAX

www.maximintegrated.com

CS Mode 4-Wire, With Busy Indicator

The 4-wire CS mode with busy indicator is shown in

Figure 11 where a single ADC is connected to an SPI-

compatible digital host with interrupt input. The corre-

sponding timing is given in Figure 12. This mode is ideally

suited for single ADC applications where the CNVST pin

may be used for low-jitter sampling while the SDI pin is

used for data readback.

With SDI high, a rising edge on CNVST completes the

acquisition, initiates the conversion and forces SDO to

high impedance. This mode requires CNVST to be held

high during the conversion and data readback phases.

Note that if CNVST and SDI are low, SDO is driven low.

During the conversion, the SDI pin can be used as a

select line for other devices on the board, but must be

returned low before the minimum conversion time and

held low until the busy signal is generated.

When the conversion is complete, SDO transitions from

high impedance to a low logic level signaling to the digital

host through the interrupt input that data readback can

commence. The MAX11152 then enters the acquisition

phase. The data bits are clocked out, MSB first, by sub-

Figure 11. CS Mode 4-Wire with Busy Indicator Connection Diagram

Figure 12. CS Mode 4-Wire with Busy Indicator Serial Interface Timing

SDO

SDI

SCLK

CLK

DATA IN

DIGITAL HOST

CNVST

CONVERT

10kΩ

OVDD

IRQ

CS1

MAX11152

SCLK

SDO

CNVST

tCONV

CONVERSION

ACQUISITION

D17

D16

tSCLK

tSCLKL

tSCLKH

tDIS

tDSDO

tSSDICNV

tHSDICNV

SDI

tACQ

tCYC

Busy Bit

tCNVPW

tHSCKCNV

tSSCKCNV

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