P60C145 datasheet(2/7 Pages) NXP

2 / 7 page

NXP Semiconductors

P60C145_SDS

SmartMX2 Family P60C145y

P60C145_SDS

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Public product data sheet

Rev. 3.0 — 27 September 2016

COMPANY PUBLIC

2 / 7

– Supporting integral concept for secure code fetch and execution

• Copy Machine offering data transfer between all Special Function Registers and all

Memory instances without CPU interaction

• Watchdog Timer supporting secure code execution, Time Stamp Counter, Real Time

Clock

• Continuous operation from 1.62 V up to 5.5 V

• Operating ambient temperature from -25 °C to +85 °C

2.3 Security features

• Outstanding Glue Logic chip layout based on the IntegralSecurity™ architecture

concept:

– Most efficient and proven protection against reverse engineering

– Impossible to recognize logical blocks by means of optical inspection

• Advanced security sensors on clock, temperature, supply voltage, light, and single fault

injection

• Active and dynamic shielding

• Advanced memory security (encryption and physical measures) for RAM, EEPROM

and ROM

• OS controlled access restriction mechanism to peripherals in user mode

• Programmable card disable feature

• Physically Unclonable Function hardware support to secure keys against new attack

scenarios

• Metal layer design for highest attack resilience

• No general standard core or re-used hard macro applied

• No use of ROM-based micro code

• Certificates and approvals; Common Criteria up to EAL6+, EMVCo

P60C145 Datasheet(PDF) 2 Page - NXP Semiconductors