8 Detailed Description

8.1 Overview

The SN74HCS245 contains 8 individual high speed CMOS transceivers with Schmitt-trigger inputs and 3-state

outputs.

Each transceiver includes one buffer oriented from Ax to Bx and one from Bx to Ax, with at least one output

disabled at all times. The direction (DIR) pin controls which buffer is active. The buffer that is not active has the

output placed into the high-impedance state.

The output enable (OE) controls all outputs in the device. When the OE pin is in the low state, the appropriate

outputs as determined by the direction (DIR) pin are enabled. When the OE pin is in the high state, all outputs of

the device are disabled. All disabled outputs are placed into the high-impedance state.

a pull-up resistor; the minimum value of the resistor is determined by the current sinking capability of the driver

and the leakage of the pin as defined in the Electrical Characteristics table. Typically a 10-kΩ resistor will be

sufficient.

8.2 Functional Block Diagram

Shared Control Logic

OE

DIR

One of Eight Transceiver Channels

Ax

Bx

Figure 8-1. Logic Diagram (Positive Logic) for SN74HCS245

8.3 Feature Description

8.3.1 CMOS IOs

This device includes CMOS IOs. These pins can be configured as either an input or an output. The output has

the balanced 3-state architecture, and the input has the Schmitt-trigger architecture.

The three states that these outputs can be in are driving high, driving low, and high impedance. The term

"balanced" indicates that the device can sink and source similar currents. The drive capability of this device

may create fast edges into light loads so routing and load conditions should be considered to prevent ringing.

Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without

being damaged. It is important for the output power of the device to be limited to avoid damage due to

overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all

times.

When the pin is configured as an input, the output is placed into a high-impedance state and it will neither source

nor sink current, with the exception of minor leakage current as defined in the Electrical Characteristics table.

In the high-impedance state, the output voltage is not controlled by the device and is dependent on external

SN74HCS245

SCLS879 – JANUARY 2022

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