MAX77504 datasheet(21/37 Pages) MAXIM

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SKIP MODE

INTERNAL CLOCK

FPWM MODE

INTERNAL CLOCK

FPWM/SYNC DEBOUNCED 0

(FPWM/SYNC = 0 FOR tDB-SKIP)

16 CONSECUTIVE

FPWM/SYNC VALID RISING

EDGES

FPWM MODE

EXTERNAL CLOCK

FPWM/SYNC = 0

FPWM/SYNC RISING EDGE

INSIDE VALID RANGE

ONE INVALID FPWM/SYNC

RISING EDGE

FPWM/SYNC RISING EDGE

FPWM/SYNC = 1

Figure 2. External Clock Synchronization Behavioral State Machine

Applications using the external synchronization function must consider minimum on-time restrictions when providing the

external clock. The Switching Frequency Selection section details these restrictions. Minimum on-time restrictions are

valid regardless of whether the switching frequency is controlled with an internal or external clock.

Buck Enable Control (EN)

Raise the EN pin voltage above VEN_HI (or tie to SUP) to enable the buck output. Lower EN to PGND to disable.

VL Regulator

An integrated 1.8V linear regulator (VL) provides power to low-voltage internal circuit blocks and switching FET gate

drivers.

SUP powers VL when VOUT is set less than the switch-over threshold (VSWO, 1.7V typical). If VOUT > VSWO, then the VL

regulator power input switches from SUP to OUT after the buck soft-start ramp finishes and POK = 1. Switching VL's input

to OUT utilizes the buck's high-efficiency to power the linear regulator (as opposed to SUP) and improves the device's

total power efficiency.

Do not load VL externally. The VL regulator activates whenever EN is high. Connect a 2.2μF ceramic capacitor from VL

to ground on the PCB.

Soft-Start

The device has an internal soft-start timer (tSS) that controls the ramp time of the output as the converter is starting.

Soft-start limits inrush current during buck startup. The converter soft-starts every time the buck enables, exits a UVLO

condition, and/or retries from an overcurrent (hiccup) or overtemperature condition. 1ms ramp time is available and only

programmable at the factory.

Power-OK (POK) Output

The device features an active-high, open-drain POK output to monitor the output voltage. POK requires an external pullup

resistor (typically 10kΩ to 100kΩ). POK goes high (high-impedance) after the buck converter output increases above

92% (VPOK_RISE) of the target regulation voltage and the soft-start ramp is done. POK goes low when the output drops

below 90% (VPOK_FALL) of target or when the buck is disabled.

MAX77504

14V Input, 3A High-Efficiency

Buck Converter in WLP or QFN

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