ST25DV64KC datasheet(73/203 Pages) STMICROELECTRONICS

73 / 203 page

Note:

There is no need of polling when writing in dynamic registers or in mailbox, since programming time is null.

Figure 34. Write cycle polling flowchart using ACK

Write cycle

in progress

Operation is

addressing the

memory

Start condition

Device select

with RW = 0

ACK

returned

YES

Stop

Data for the

Write operation

Send Address

and Receive ACK

YES

StartCondition

Continue the

Write operation

Continue the

Random Read operation

Device select

with RW = 1

First byte of instruction

with RW = 0 already

decoded by the device

6.5

I²C read operations

Read operation in user memory is performed successfully only if:

•

Area to which the byte belongs is not read protected by the I2CSS register.

•

Area to which the byte belongs is read protected by the I2CSS register, but I²C security session is open.

Read operations in system memory and dynamic registers are done independently of any protection mechanism,

except I2C_PWD register which needs I²C security session to be open first.

Read operation in fast transfer mode’s mailbox is performed successfully only if fast transfer mode is activated.

If read is not successful, ST25DVxxKC releases the bus and I²C host reads byte value FFh.

After the successful completion of a read operation, the device’s internal address counter is incremented by one,

to point to the next byte address.

After an unsuccessful read operation, ST25DVxxKC enters in I²C dead state: internal address counter is not

incremented, and ST25DVxxKC is waiting for a full new I²C instruction.

ST25DV04KC ST25DV16KC ST25DV64KC

I²C read operations

DS13519 - Rev 3

page 73/203

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