@vic
AV93LC46
Copyright © Avic Electronics Corp.
5
Website: http://www.avictek.com
Functional Descriptions
Applications
The AV93LC46 is ideal for high volume applications requiring low power and low density storage. This
device uses a low cost, space saving 8-pin package. Typical applications include robotics, alarm devices,
electronic locks, meters and instrumentation settings such as LAN cards, monitors and MODEM.
Endurance and Data Retention
The AV93LC46 is designed for applications requiring up to 1000K programming cycles (WRITE,
WRALL, EARSE and ERAll). It provides 40 years of secure data retention without power after the
execution of 1000K programming cycles.
Device Operation
The AV93LC46 is controlled by seven 9-bit instructions. Instructions are clocked in (serially) on the DI
pin.
Each instruction begins with a logical “1” (the start bit). This is followed by the opcode (2 bits), the
address field (6 bits), and data, if appropriate. The clock signal (SK) may be halted at any time and the
AV93LC46 will remain in its last state. This allows full static flexibility and maximum power
conservation.
Read (READ)
The READ instruction is the only instruction that outputs serial data on the DO pin. After the read
instruction and address have been decoded, data is transferred from the selected memory register into a 16-
bit serial shift register. (Please note that one logical “0” bit precedes the actual 16-bit output data string.)
the output on DO changes during the rising edge transitions of SK. (Shown in Figure 3 )
Auto Increment Read Operations
Sequential read is possible, since the AV93LC46 has been designed to output a continuous stream of
memory content in response to a single read operation instruction. To utilize this function, the system
asserts a read instruction specifying a start location address. Once the 16 bits of the addressed word have
been clocked out, the data in consecutively higher address locations (the address “0000” is assumed as the
higher address of “111111”) is output. The address will wrap around continuously with CS high until the
chip select (CS) control pin is brought low. This allows for single instruction data dumps to executed with
a minimum of firmware overhead.
Write Enable (WEN)
Before any device programming (WRITE, WRAll, ERASE, and ERAl) can be done, the WRITE ENABLE
(WEN) instruction must be executed first. When Vcc is applied, this device powers up in the WRITE
DISABLE state. The device then remains in a WRITE DISABle state until a WEN instruction is executed.
Thereafter the device remains enabled until a WDS instruction is executed or until Vcc is removed.
(NOTE: Neither the Wen nor the WDS instruction has any effect on the READ instruction.) (Shown in
Figure 4.)
Write Disable (WDS)
The WRITE DISABLE (WDS) instruction disables all programming capabilities. This protects the entire
part against accidental modification of data until a WEN instruction is executed. (When Vcc is applied, this
part powers up in the WRITE DISABLE state.) To protect data, a WDS instruction should be executed
upon completion of each programming operation. (NOTE: Neither the WEN nor the WDS instruction has
any effect on the READ instruction.) (Shown in Figure 5.)
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