HT48E70 datasheet(21/44 Pages) HOLTEK

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HT48E70

Rev. 1.00

September 16, 2005

ERAL

The ERAL instruction erases the entire 256

´8 memory

cells to a logical

²1² state in the programming enable

mode. After the erase-all instruction set has been is-

sued, the data erase feature is activated by a falling

edge of CS. Since the internal auto-timing generator

provides all timing signal for the erase-all operation, so

the SK clock is not required. During the internal erase-all

operation, we can verify the busy/ready status if CS is

high. The DO will remain low but when the operation is

over, the DO will return to high and further instruction

can be executed.

WRAL

The WRAL instruction writes data into the entire 256

´8

memory cells in the programming enable mode. After

the write-all instruction set has been issued, the data

writing is activated by a falling edge of CS. Since the in-

ternal auto-timing generator provides all timing signals

for the write-all operation, so the SK clock is not re-

quired. During the internal write-all operation, we can

verify the busy/ready status if CS is high. The DO will re-

main low but when the operation is over the DO will re-

turn to high and further instruction can be executed.

EECR Control Timing Diagrams

· READ

· EWEN/EWDS

· WRITE

C S

S K

D O

D I

S t a r t b i t

( 1 )

t C D S

* A d d r e s s p o i n t e r a u t o m a t i c a l l y c y c l e s t o t h e n e x t w o r d

A N

A 0

D 0 D X

D X

M o d e

A N

D X

( X 8 )

A 7

D 7

C S

S K

S t a n d b y

D I

( 1 )

S t a r t b i t

1 1 = E W E N

0 0 = E W D S

C S

S K

D O

S t a n d b y

D I

( 1 )

t S V

t P R

t C D S

V e r i f y

B u s y

R e a d y

S t a r t b i t

A N A N - 1 A N - 2

A 1

D 0

A 0

D X

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