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M76DW52003BA Datasheet(PDF) 18 Page - STMicroelectronics |
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M76DW52003BA Datasheet(HTML) 18 Page - STMicroelectronics |
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18 / 27 page ![]() M76DW52003TA, M76DW52003BA 18/27 Figure 11. SRAM Write AC Waveforms, W Controlled Note: 1. W, E1S, E2S, UBS and/or LBS must be asserted to initiate a write cycle. Output Enable (G) = Low (otherwise, DQ0-DQ15 are high impedance). If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance. 2. The I/O pins are in output mode and input signals must not be applied. AI07944b tAVAV tWHAX tDVWH INPUT VALID A0-A17 E1S W DQ0-DQ15 VALID E2S tAVWH tBLWH tGHQZ tWHDZ tAVWL UBS, LBS tE2HWH tE1LWH G tWLWH Note 2 |
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