TMS28F004AXY datasheet(16/80 Pages) TI

16 / 80 page

TMS28F004Axy, TMS28F400Axy

524288 BY 8-BIT/262144 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS829A – JANUARY 1996 – REVISED AUGUST 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

reset / deep power-down mode (continued)

If RP goes low during a program or erase operation, the device powers down and, therefore, becomes

nonfunctional. Data being written or erased at that time becomes invalid or indeterminate, requiring that the

operation be performed again after power restoration.

power-supply detection

RP must be connected to the system reset / power good signal to ensure that proper synchronization is

maintained between the CPU and the flash memory operating modes. The default state after power up and exit

from deep power-down mode is read array. RP also is used to indicate that the power supply is stable so that

the operating supply voltage can be established (3 V, 3.3 V or 5 V). Figure 10 shows the proper power-up

sequence. To reset the operating supply voltage, the device must be completely powered off (VCC = 0 V) before

the new supply voltage is detected.

TMS28F004AXY Datasheet(PDF) 16 Page - Texas Instruments