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PCA9614DPZ Datasheet(PDF) 2 Page - NXP Semiconductors

Part # PCA9614DPZ
Description  2-channel multipoint Fast-mode Plus differential I2C-bus buffer
PDF  28 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCA9614DPZ Datasheet(HTML) 2 Page - NXP Semiconductors

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NXP Semiconductors
PCA9614
2-channel multipoint Fast-mode Plus differential I2C-bus buffer
VDD(A)1
SCL
SDA
PCA9614
aaa-011060
dI2C-bus
(differential I2C-bus,
1 of 2 lines shown)
twisted-pair cable
single-ended
I2C-bus
PCA9614
SCL
SDA
GND1
GND2
VDD(A)2
single-ended
I2C-bus
VDD(B)
VDD(B)
EN
EN
VDD(B)
VDD(B)
Figure 1. SMBus/I2C-bus translation to dI2C-bus and back to SMBus/I2C-bus
2 Features and benefits
• New dI2C-bus buffers offer improved resistance to system noise and ground offset up
to 1⁄2 of supply voltage
• 2 channel dI2C (differential I2C) to Fm+ single-ended buffer operating up to 1 MHz with
30 mA SDA/SCL drive capability
• Compatible with I2C-bus Standard/Fast-mode and SMBus, Fast-mode Plus up to 1
MHz
• Active HIGH (internal pull-up resistor) Enable disables devices to high-impedance state
• Single-ended I2C-bus on card side up to 540 pF
• Differential I2C-bus on cable side supporting multi-drop bus
– Maximum cable length: 3 m (approximately 10 feet) (longer at lower frequency)
– dI2C output: 1.5 V differential output with nominal terminals
– Differential line impedance (user defined): 100 Ω nominal suggested
– Receive input sensitivity: ±200 mV
– Hysteresis: ±30 mV typical
– Input impedance: high-impedance (1 MΩ typical)
– Receive input voltage range: -0.5 V to +5.5 V
• Lock-up free operation
• Supports arbitration and clock stretching across the dI2C-bus buffers
• Powered-off and powering-up high-impedance I2C-bus pins
• Operating supply voltage (VDD(A)) range of 2.3 V to 5.5 V with single-ended side 5.5 V
tolerant
• Differential I2C-bus operating supply voltage (VDD(B)) range of 3.0 V to 5.5 V with 5.5 V
tolerant. Best operation is at 5 V.
• ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
• Package offering: TSSOP10
PCA9614
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 21 September 2021
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