10 Power Supply Recommendations

midsupply. The device also operates using power supplies from ±4 V (8 V) to ±18 V (36 V) and non-midsupply

input and output common-mode voltages with excellent performance.

11 Layout

11.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use

good printed circuit board (PCB) layout practices, including:

• To avoid converting common-mode signals into differential signals and thermal electromotive forces (EMFs),

make sure that both input paths are symmetrical and well-matched for source impedance and capacitance.

• As shown in Figure 11-1, keep the external gain resistor close to the RG pins to keep the loop inductance as

low as possible and to avoid a potential parasitic coupling path. Even slight mismatch in parasitic capacitance

at the gain setting pins can degrade CMRR over frequency. In applications that implement gain switching

capacitance is as small as possible, and most importantly, so that capacitance mismatch between the RG

pins is minimized.

• Noise can propagate into analog circuitry through the power pins of the device and of the circuit as a whole.

Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog

circuitry.

– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces.

If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in

parallel with the noisy trace.

• Leakage on the FDA_IN+ and FDA_IN– pins can cause in a dc offset error in the output voltages.

Additionally, excessive parasitic capacitance at these pins can result in decreased phase margin and affect

the stability of the output stage. If not using these pins to implement deliberate capacitive feedback, follow

best practices to minimize leakage and parasitic capacitance, which may include implementing keep-out

areas in any ground planes that lie immediately below the pins.

• Minimize the number of thermal junctions. Ideally, the signal path is routed within a single layer without vias.

• Keep sufficient distance from major thermal energy sources (circuits with high power dissipation). If not

possible, place the device so that the effects of the thermal energy source on the high and low sides of the

differential signal path are evenly matched.

• Solder the thermal pad to the PCB. For the INA851 to properly dissipate heat, connect the thermal pad

to a plane or large copper pour that is either floating or electrically connected to VS–, even for low-power

applications.

• Keep the traces as short as possible.

INA851

SBOS999 – MARCH 2022

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