ADAQ7980 datasheet(3/35 Pages) AD

3 / 35 page

Data Sheet

ADAQ4003

Rev. 0 | Page 3 of 35

SPECIFICATIONS

VDD = 1.8 V ± 5%, VS+ = 5.5 V ± 5%, VS− = 0 V, VIO = 1.7 V to 5.5 V, reference voltage (VREF) = 5 V, sampling frequency (fS) =

2 MSPS, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, and turbo mode enabled, unless otherwise

noted. ADC driver configured in single-ended to differential configuration and fast mode, unless otherwise noted.

Table 2.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

RESOLUTION

Bit

ANALOG INPUTS

IN+, IN−, R1K1+, R1K1−, R1K+, and R1K−

Input Impedance (ZIN)

Single-ended to differential configuration

G = 0.454, input voltage (VIN) = 22 V p-p

1.3

kΩ

G = 0.909, VIN = 11 V p-p

1.44

kΩ

G = 1, VIN = 10 V p-p

1.33

kΩ

G = 1.9, VIN = 5.2 V p-p

778

Fully differential configuration

G = 0.454 and G = 0.909,

VIN = 22 V p-p and 11 V p-p

1.1

kΩ

G = 1, VIN = 10 V p-p

kΩ

G = 1.9, VIN = 5.2 V p-p

523

Differential Input Voltage Ranges1

G = 0.454, VIN = 22 V p-p

−2.2 × VREF

+2.2 × VREF

G = 0.909, VIN = 11 V p-p

−1.1 × VREF

+1.1 × VREF

G = 1, VIN = 10 V p-p

−VREF

+VREF

G = 1.9, VIN = 5.2 V p-p

−0.526 × VREF

+0.526 × VREF

Input Capacitance

IN+ and IN−

THROUGHPUT

Complete Cycle

500

Conversion Time

290

320

Acquisition Phase2

290

Throughput Rate3

MSPS

Transient Response4

μs

DC ACCURACY

Single-ended to differential configuration

No Missing Codes

Bits

Integral Linearity Error (INL)

All gains, VS− = −1 V

−8

±3

ppm

−2.1

±0.8

+2.1

LSB5

Differential Linearity Error (DNL)

All gains, VS− = −1 V

−1

±0.4

LSB5

−3.8

±2.66

+3.8

ppm

Transition Noise

All gains

0.93

LSB

Gain Error

All gains

−0.05

±0.005

+0.05

%FS

Gain Error Drift

All gains

−3

±0.5

ppm/°C

Offset Error

G = 0.454

−1

±0.1

G = 0.909, G = 1

−0.9

±0.06

+0.9

G = 1.9

−1.5

±0.01

+1.5

Offset Error Drift

G = 0.454

−8

+0.7

ppm/°C

G = 0.909 and G = 1

−10

+1.6

+10

ppm/°C

G = 1.9

−15

+2.6

+15

ppm/°C

Common-Mode Rejection Ratio (CMRR)

Fully differential configuration, all gains

Power Supply Rejection Ratio (PSRR)

Positive

VDD = 1.71 V to 1.89 V

VS+ = 5.225 V to 5.775 V, VS− = 0 V

110

Negative

VS+ = +5.5 V, VS− = 0 V to −0.5 V

107

1/f Noise6

Bandwidth = 0.1 Hz to 10 Hz

μV p-p

Input Current Noise

Input frequency (fIN) = 100 kHz

pA/√Hz

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