ADAQ4003

Data Sheet

Rev. 0 | Page 26 of 35

STATUS WORD

The 6-bit status word can be appended to the end of a conversion

result, and the default conditions of these bits are shown in

Table 15. The status bits must be enabled in the register setting.

When the OV clamp flag is 0, this bit indicates an overvoltage

condition. The OV clamp flag status bit updates on a per

conversion basis.

The SDO line returns to high impedance after the sixth status

bit is clocked out (except in daisy-chain mode). The user is not

required to clock out all status bits to start the next conversion.

The serial interface timing for CS mode, 3-wire without busy

indicator, including status bits, is shown in Figure 54.

Table 15. Status Bits (Default Conditions)

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OV clamp flag

Span compression

High-Z mode

Turbo mode

Reserved

Reserved

SDO

D17

D16

D15

D1

D0

SCK

1

2

3

16

17

18

CN V

CONVERSION

ACQUISITION

ACQUISITION

SDI = 1

ACQ

23

24

STATUS BITS B[5:0]

B1

B0

22

Figure 54. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram Including Status Bits (SDI High)