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ADE7978ACPZ-RL Datasheet(PDF) 81 Page - Analog Devices |
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ADE7978ACPZ-RL Datasheet(HTML) 81 Page - Analog Devices |
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81 / 125 page  Data Sheet ADE7978/ADE7933/ADE7932/ADE7923 Rev. D | Page 81 of 125 USING THE INTERRUPTS WITH AN MCU Figure 101 shows a timing diagram for a suggested implementation of ADE7978 interrupt management using an MCU. At Time t1, the IRQx pin goes low, indicating that one or more interrupt events have occurred in the ADE7978. After the IRQx pin goes low, the following steps take place: 1. Tie the IRQx pin to a negative edge triggered external interrupt on the MCU. 2. Configure the MCU to start executing its interrupt service routine (ISR) when it detects the negative edge. 3. When the MCU starts executing the ISR, disable all interrupts using the global interrupt mask bit. The MCU external interrupt flag can now be cleared to capture interrupt events that occur during the current ISR. 4. When the MCU interrupt flag is cleared, read STATUSx, the interrupt status register. The interrupt status register contents are used to determine the source of the interrupts and, therefore, the appropriate action to take. 5. Write back the same STATUSx contents to the ADE7978 to clear the status flags and reset the IRQx line to logic high (t2). If a subsequent interrupt event occurs during the ISR (t3), that event is indicated by the MCU external interrupt flag being set again. On returning from the ISR, the global interrupt mask bit is cleared in the same instruction cycle, and the external interrupt flag uses the MCU to jump to its ISR again. This action ensures that the MCU does not miss any external interrupts. Figure 102 shows a recommended timing diagram when the status bits in the STATUSx registers work in conjunction with bits in other registers. When the IRQx pin goes low, the STATUSx register is read, and if one of these bits is set to 1, a second status register is read immediately to identify the phase that triggered the interrupt. In Figure 102, PHx denotes the PHNOLOAD, PHSTATUS, IPEAK, VPEAK, or PHSIGN register. After reading the PHx register, the STATUSx register is written back to clear the status flags. JUMP TO ISR GLOBAL INTERRUPT MASK CLEAR MCU INTERRUPT FLAG READ STATUSx JUMP TO ISR WRITE BACK STATUSx ISR ACTION (BASED ON STATUSx CONTENTS) ISR RETURN GLOBAL INTERRUPT MASK RESET MCU INTERRUPT FLAG SET PROGRAM SEQUENCE t2 t1 t3 IRQx Figure 101. Interrupt Management PROGRAM SEQUENCE IRQx JUMP TO ISR GLOBAL INTERRUPT MASK CLEAR MCU INTERRUPT FLAG READ STATUSx READ PHx JUMP TO ISR WRITE BACK STATUSx ISR ACTION (BASED ON STATUSx CONTENTS) ISR RETURN GLOBAL INTERRUPT MASK RESET MCU INTERRUPT FLAG SET t2 t1 t3 Figure 102. Interrupt Management When PHSTATUS, IPEAK, VPEAK, or PHSIGN Register Is Involved |
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