ADE7933ARIZ datasheet(100/125 Pages) AD

100 / 125 page

ADE7978/ADE7933/ADE7932/ADE7923

Data Sheet

Rev. D | Page 100 of 125

SPI-COMPATIBLE INTERFACE

The SPI interface of the ADE7978 is always a slave in the

communication and consists of four pins (with dual functions):

SCLK/SCL, MOSI/SDA, MISO/HSD, and SS/HSA. The functions

used in the SPI-compatible interface are SCLK, MOSI, MISO,

and SS.

The serial clock for a data transfer is applied at the SCLK logic

input. All data transfer operations are synchronized to the serial

clock. The maximum serial clock frequency supported by the

SPI interface is 2.5 MHz.

Data shifts into the ADE7978 at the MOSI logic input on the

falling edge of SCLK, and the ADE7978 samples it on the rising

edge of SCLK. Data shifts out of the ADE7978 at the MISO

logic output on the falling edge of SCLK and is sampled by the

master device on the rising edge of SCLK. The most significant

bit of the word is shifted in and out first. MISO stays in high

impedance when no data is transmitted from the ADE7978.

Figure 128 shows the connection between the ADE7978 SPI

interface and a master device that contains an SPI interface.

MOSI

MISO

SCLK

ADE7978

MOSI

MISO

SCK

SPI DEVICE

Figure 128. Connecting the ADE7978 SPI Interface to an SPI Device

The SS logic input is the chip select input. This input is used when

multiple devices share the serial bus. Drive the SS input low for

the entire data transfer operation. Bringing SS high during a data

transfer operation aborts the transfer and places the serial bus in a

high impedance state. A new transfer can be initiated by returning

the SS logic input low. However, aborting a data transfer before

completion leaves the accessed register in a state that cannot be

guaranteed. Every time a register is written, its value should be

verified by reading it back. The protocol is similar to the protocol

used in the I2C interface.

SPI Write Operation

A write operation using the SPI interface of the ADE7978 is

initiated when the master sets the SS pin low and begins sending

one byte, representing the slave address of the ADE7978, on the

MOSI line (see Figure 129). The master sends data on the MOSI

line starting with the first high to low transition of SCLK. The

SPI interface of the ADE7978 samples the data on the low to high

transitions of SCLK.

The most significant seven bits of the address byte can have any

value, but as a good programming practice, these bits should have

a value other than 0111000, which is the 7-bit address used in the

I2C protocol. Bit 0 of the address byte is the read/write bit. For a

write operation, Bit 0 must be cleared to 0. The master then sends

the 16-bit address of the register that is to be written followed

by the 32-, 16-, or 8-bit value of that register without losing an

SCLK cycle. After the last bit is transmitted, the master sets the

SS and SCLK lines high at the end of the SCLK cycle, and the

communication ends. The data lines, MOSI and MISO, enter a

high impedance state.

15 14

SCLK

MOSI

0 31 30

Figure 129. SPI Write Operation of a 32-Bit Register

ADE7933ARIZ Datasheet(PDF) 100 Page - Analog Devices

ADE7933ARIZ Datasheet(HTML) 100 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL