ADE7932ARIZ datasheet(21/125 Pages) AD

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Data Sheet

ADE7978/ADE7933/ADE7932/ADE7923

Rev. D | Page 21 of 125

Pin No.

Mnemonic

Description

MISO/HSD

Data Output for the SPI Port/Data Output for the HSDC Port.

MOSI/SDA

Data Input for the SPI Port/Data Output for the I2C Port. The default functionality of this pin is SDA.

GND

Ground Reference for the Input Circuitry.

VDD

Supply Voltage. This pin provides the supply voltage. For specified operation, maintain the supply voltage at

3.3 V ± 10%. Decouple this pin to GND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.

LDO

1.8 V Output of the Digital Low Dropout (LDO) Regulator. Decouple this pin with a 4.7 µF capacitor in parallel

with a ceramic 100 nF capacitor. Do not connect active external circuitry to this pin.

DGND

Ground Reference for the Digital Circuitry.

XTALOUT

A crystal with a maximum drive level of 0.5 mW and an equivalent series resistance (ESR) of 20 Ω can be

connected across this pin and the XTALIN pin to provide a clock source for the ADE7978.

XTALIN

Master Clock. An external clock can be provided at this logic input. Alternatively, a crystal with a maximum

drive level of 0.5 mW and an ESR of 20 Ω can be connected across XTALIN and XTALOUT to provide a clock

source for the ADE7978. The clock frequency for specified operation is 16.384 MHz. For more information, see

the ADE7978, ADE7933/ADE7932, and ADE7923 Clocks section.

ZX/DREADY

Zero-Crossing (ZX) Output Pin. The ZX pin goes high on the positive-going edge of the selected phase voltage

zero crossing; the pin goes low on the negative-going edge of the zero crossing (see the Zero-Crossing

Detection section for more information).

DREADY is an active low signal that is generated approximately 70 ns after Bit 17 (DREADY) in the STATUS0 register

is set to 1. This pin has a frequency of 8 kHz and stays low for 10 µs every period. The default functionality of

this pin is DREADY.

VT_A

Selects the second voltage input (V2P) or the temperature measurement on the Phase A ADE7933/ADE7932.

Connect this pin to the V2/TEMP pin of the Phase A ADE7933/ADE7932. If no ADE7933/ADE7932 is used to

sense Phase A, leave this pin unconnected.

DATA_A

Receives the bit streams from the Phase A ADE7933/ADE7932. Connect this pin to the DATA pin of the Phase A

ADE7933/ADE7932. If no ADE7933/ADE7932 is used to sense Phase A, connect this pin to VDD.

Exposed Pad. Create a similar pad on the PCB under the exposed pad. Solder the exposed pad to the pad on

the PCB to confer mechanical strength to the package. Connect the pads to DGND and GND.

ADE7932ARIZ Datasheet(PDF) 21 Page - Analog Devices

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