SIP32408 datasheet(10/15 Pages) VISHAY

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SiP32408, SiP32409

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Vishay Siliconix

S20-0528-Rev. G, 06-Jul-2020

Document Number: 63717

For technical questions, contact: powerictechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

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It then follows that, assuming an ambient temperature of

70 °C, the maximum power dissipation will be limited to

about 324 mW.



So long as the load current is below the 3.5 A limit, the

maximum continuous switch current becomes a function of

two things: the package power dissipation and the RDS(on) at

the ambient temperature.



As an example let us calculate the worst case maximum

load current at TA = 70 °C. The worst case RDS(on) at 25 °C

occurs at an input voltage of 1.2 V and is equal to 52 m

.

The RDS(on) at 70 °C can be extrapolated from this data using

the following formula:



RDS(on) (at 70 °C) = RDS(on) (at 25 °C) x (1 + TC x DT)

Where TC is 3300 ppm/°C. Continuing with the calculation

we have



RDS(on) (at 70 °C) = 52 m x (1 + 0.0033 x (70 °C - 25 °C))

= 60 m



The maximum current limit is then determined by

which in this case is 2.3 A. Under the stated input voltage

condition, if the 2.3 A current limit is exceeded the internal

die temperature will rise and eventually, possibly damage

the device.

Active EN Pull Down for Reverse Blocking

When an internal circuit detects the condition of VOUT 0.8 V

higher than VIN, it will turn on the pull down circuit connected

to EN, forcing the switching off. The pull down value is about

1 k

.

Pulse Current Capability

The device is mounted on the evaluation board shown in the

PCB layout section. It is loaded with pulses of 5 A and 1 ms

for periods of 4.6 ms.



SiP32408 and SiP32409 can safely support 5 A pulse

current repetitively at 25 °C.

Switch Non-Repetitive Pulsed Current

SiP32408 and SiP32409 can withstand inrush current of up

to 12 A for 100 μs at 25 °C when heavy capacitive loads are

connected and the part is already enabled.

Recommended Board Layout

For the best performance, all traces should be as short as

possible to minimize the inductance and parasitic effects.

The input and output capacitors should be kept as close

as possible to the input and output pins respectively.



Connecting the central exposed pad to GND, using wide

traces for input, output, and GND help reducing the case to

ambient thermal impedance.

)

(

(max.)

LOAD

OUT

Reverse

Blocking

Charge

Pump

Control Logic

Input Buffer

Pull Down

Circuit

Control and Drive

OUT > VIN

Detect

When V

OUT is 0.8 V above the VIN, pull down circuit

will be activated. It connects the EN to GND with a

resistance of around 1 k

Ω.

5 A

1 ms

180 mA

4.6 ms

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