SIC474 datasheet(21/26 Pages) VISHAY

21 / 26 page

SiC471, SiC472, SiC473, SiC474

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Vishay Siliconix

Work-In-Progress

SPending-Rev. A, 04-Jul-2018

Document Number: 75786

For technical questions, contact: powerictechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

PCB LAYOUT RECOMMENDATIONS

Step 1: VIN/GND Planes and Decoupling

Fig. 56

1. Layout VIN and PGND planes as shown above

2. Ceramic capacitors should be placed between VIN and

PGND, and very close to the device for best decoupling

effect

3. Various ceramic capacitor values and package sizes

should be used to cover entire coupling spectrum

e.g. 1210 and 0603

4. Smaller capacitance values, closer to VIN pin(s), provide

better high frequency response

Step 2: VCIN Pin

Fig. 57

1. VCIN is the input pin for both internal LDO and tON block.

tON varies with input voltage and it is necessary to put a

decoupling capacitor close to this pin

2. The connection can be made through a via and the

capacitor can be placed at bottom layer



Step 3: SW Plane

Fig. 58

1. Connect output inductor to device with large plane to

lower resistance

2. If

any

snubber

network

required,

place

the

components on the bottom side as shown above

Step 4: VDD/VDRV Input Filter

Fig. 59

1. CVDD cap should be placed between VDD and AGND to

achieve best noise filtering

2. CVDRV cap should be placed close to VDRV and PGND pins

to reduce effects of trace impedance and provide

maximum instantaneous driver current for low side

MOSFET during switching cycle



VIN

VSWH

VIN Plane

PGND Plane

Vcin decouple cap

AGND Plane

PGND Plane

VSWH

AGND

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