NBP9 datasheet(8/61 Pages) NXP

8 / 61 page

NXP Semiconductors

NBP9

Battery pressure monitor sensor

Description

Remarks

PWM (PTA4)

When applicable, a PWM signal is

generated on the PWM pin. The PWM

duty cycle depends on the status flags

and pressure value.

This pin has an internal pull-up to

prevent unwanted BACKGROUND

DEBUG mode entry. The External host

must let the pin float or connect it to

a pull-up that is parallel to the NBP9

internal pull-up. There must be no pull-

down enabled or connected to this pin.

Note: When the NBP9 is in sleep mode, the CS_B/WAKEUP pin is configured as input with pull-up enabled. All other pins

are in high impedance state, which means that the NBP9 does not maintain their levels. Specifically, the level of the PS

ENABLE pin is not maintained by the NBP9 in sleep, so when this signal is used, its idle level must be maintained by an

external circuit.

Note: If the external host will be switched off, the CS_B/WAKE UP signal must be isolated to prevent inadvertent

assertion; a fixed low level at the NBP9 CS_B/WAKE UP input will cause the sensor to remain waiting for the SPI SCLK,

and not collect new pressure measurements.

Table 4. Connection pins description...continued

6.2 Serial peripheral interface (SPI) module

The SPI module is configured as a standard client SPI which allows a full duplex,

synchronous, serial communication between the unit and a server SPI device.

The principal features of the SPI block are summarized as follows:

• Client only mode operation.

• Full-duplex, 4 wire, synchronous serial communication.

• Command-Response communication format.

• SCLK operation up to 10 MHz supported.

• Fixed Clock polarity and phase supported (CPOL=0, CPHA = 0).

– The SPI module requires the base clock value to be at the low state (CPOL = 0) with

data captured on the rising edge of the clock and data propagated on the falling edge

of the clock (CPHA = 0).

• Supports 8-bit register read and write operations via 16 clock transfers.

• Even Parity error-checking.

• Alternate bus controller for the system-on-chip (SoC) internal IP Bus system.

– SPI can be used to access the entire Memory map of the NBP9.

• Contains eight, 8-bit memory mapped registers for user and test mode operations.

• Decodes SPI test mode entry sequence and enables SPI test mode.

As a client, the SPI interface is compatible with SPI interface mode 00, corresponding

to CPOL = 0 and CPHA = 0. For CPOL = 0, the idle value of the clock is zero, and the

active value of the clock is 1. For CPHA = 0, data is captured on the rising edge (low

to high transition) of the clock and data is propagated on the falling edge (high to low

transition) of the clock.

As a client, the CS_B pin is driven low at the start of a transaction, held low during

the transfer, and then driven high again after the transaction is completed. During a

transaction, the server toggles the clock (SCLK). The SCLK polarity is defined as having

an idle value that is low, and an active phase that is high (CPOL = 0). Serial input and

output data is captured on the rising edge of the clock and propagated on the falling

edge (CPHA = 0). Single-byte read and single-byte write operations are completed

in two strobes of CS_B of 16 SCLK cycles each; multiple byte reads and writes are

completed in additional multiples of 16 SCLK cycles. The first SCLK cycle latches the

most significant bit on SOCI to select whether the desired operation is a read (R/W = 1)

NBP9

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.4 — 11 March 2022

8 / 61

NBP9 Datasheet(PDF) 8 Page - NXP Semiconductors

NBP9 Datasheet(HTML) 8 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

Datasheet Download

Link URL