NC

NC

CAP

SOIC-14

S1

V+

G1

NC

IN

EN

GND

G2

FAULT

Top View

11

12

13

14

2

3

4

1

8

9

10

5

6

7

Si9976

Vishay Siliconix

www.vishay.com

4

Document Number: 70016

S-40757—Rev. F, 19-Apr-04

PIN CONFIGURATION AND ORDERING INFORMATION

ORDERING INFORMATION

Part Number

Temperature Range

Package

Si9976DY

Si9976DY-T1

−40 to 85_C

SOIC-14

Si9976DY-T1—E3

PIN DESCRIPTION

Pin 1

No connection.

Pin 2: CAP

Connection for the positive terminal of the bootstrap capacitor

applications.

Pin 3: V+

This is the only external power supply required for the Si9976,

and must be the same supply used to power the half-bridge it

is driving. The Si9976 powers it’s low-voltage logic, low-side

gate driver, and bootstrap/charge pump circuits from

self-contained voltage regulators which require only a

bootstrap capacitor on the CAP pin and a bypass capacitor on

No voltage sensing circuitry monitors V+ directly; however, the

bootstrap voltage (which are derived from V+) are directly

protected by undervoltage monitors.

Connection to the internally generated low-voltage supply

which must be bypassed to ground with a 0.01-mF capacitor.

Pin 5: IN

Logic input. A low level input turns off the high-side half-bridge

MOSFET and, after an internally set dead time, turns the

low-side half-bridge MOSFET on. A high input level has the

opposite effect. The input is compatible with 5-, 12- or 15-V

logic outputs.

Pin 6: EN

Enable input. A low EN input level prevents turn on of either

half-bridge MOSFET. If the Si9976 is internally disabled as a

result of an output short-circuit condition, a low-to-high

transition on EN is required to clear the fault and resume

operation. The input logic levels are the same as IN.

the logic supply voltage in order to set the high level of the

FAULT output. If the FAULT output is not used, this pin may be

left open with no effect on internal fault sensing or protection

circuitry.

Pin 8: FAULT

The Fault output is latched high when a short-circuit output

condition is detected. FAULT will return low when the circuit is

reset using the EN pin. The FAULT output also indicates the

fault condition is cleared automatically when the undervoltage

condition clears.

Pin 9: G2

This pin drives the gate of the external low-side power

transistor.

Pin 10: GND

The ground return for V+, logic reference, and connection for

source of external low-side power transistor.

Pin 11

No connection.

Pin 12: G1

This pin drives the gate of the external high side power

transistor.

Pin 13: S1

Connection for the source of the external high-side power

transistor, the drain of the external low-side power transistor,

the negative terminal of the bootstrap capacitor, and the

system load. The voltage on this pin is sensed by the circuitry

that monitors the load for shorts.

Pin 14

No connection.