MCP79520 datasheet(43/58 Pages) MICROCHIP

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DS20002300D-page 43

MCP7951X/MCP7952X

6.4.2

PROTECTED EEPROM UNLOCK

SEQUENCE

The protected EEPROM block requires a special

unlock sequence to prevent unintended writes, utilizing

the UNLOCK instruction.

Before performing the unlock sequence, the WEL bit

must first be set by executing an EEWREN instruction

(see Section 6.3.1 “Write Enable and Write Disable”

for details).

To unlock the block, the following sequence must be

followed after setting the WEL bit:

Execute an UNLOCK instruction with a data byte

of 0x55

Execute an UNLOCK instruction with a data byte

of 0xAA

Write the desired data bytes to the protected

EEPROM using the IDWRITE instruction

Figure 6-12 illustrates the sequence.

An entire protected EEPROM page does not have to be

written in a single operation. However, the block is

locked after each write operation and must be unlocked

again to start a new Write command.

6.4.3

PROTECTED EEPROM WRITE

SEQUENCE

Prior to any attempt to write data to the MCP795XX

protected EEPROM block, the write enable latch must

be set by issuing the EEWREN instruction and then the

protected EEPROM unlock sequence must be

performed. The EEWREN instruction is issued by setting

CS low and then clocking out the proper instruction into

the MCP795XX. After all eight bits of the instruction are

transmitted, CS must be driven high to set the write

enable latch.

After setting the write enable latch and performing the

unlock sequence, the user may proceed by driving CS

low, issuing an IDWRITE instruction, followed by the

address and then the data to be written. Up to 8 bytes

of data can be sent to the device before a write cycle is

necessary. The only restriction is that all of the bytes

must reside in the same page. Additionally, a page

address begins with XXXX x000 and ends with

XXXX x111. If the internal address counter reaches

XXXX x111 and clock signals continue to be applied to

the chip, the address counter will roll back to the first

address of the page and over-write any data that

previously existed in those locations.

For the data to be actually written to the array, the CS

must be brought high after the Least Significant bit (D0)

of the nth data byte has been clocked in. If CS is driven

high at any other time, the write operation will not be

completed. Refer to Figure 6-12 for more detailed

illustrations on the page write sequence. While the

write is in progress, the STATUS register may be read

to check the status of the WIP, WEL, BP1 and BP0 bits.

Attempting to read a memory array location will not be

possible during a write cycle. Polling the WIP bit in the

STATUS register is recommended in order to

determine if a write cycle is in progress. When the write

cycle is completed, the write enable latch is reset.

If an attempt is made to write to an address outside of

the 0x00 to 0x0F range, the MCP795XX will not

execute the WRITE instruction, no data will be written,

and the device will immediately accept a new

command.

Note 1: Diverging from any step of the unlock

sequence may result in the EEPROM

remaining locked, the write operation

being ignored and the WEL bit being

reset.

2: Unlocking the EEPROM is not required in

order to read from the memory.

Note:

Protected EEPROM write operations are

limited to writing bytes within a single

physical page, regardless of the number

of bytes actually being written. Physical

page boundaries start at addresses that

are integer multiples of the page buffer

size (or ‘page size’) and end at addresses

that are integer multiples of page size – 1.

If an IDWRITE command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being written to the next page as might be

expected. It is therefore necessary for the

application software to prevent protected

EEPROM write operations that would

attempt to cross a page boundary.

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