5

TYPICAL SYSTEM OPERATION

The MSK 4422 is designed to be used with a +100 volt high voltage bus, +15 volt low power bus and +5 volt

logic signals. Proper derating should be applied when designing the MSK 4422 into a system. High frequency layout

techniques with ground planes on a printed circuit board is the only method that should be used for circuit construc-

tion. This will prevent pulse jitter caused by excessive noise pickup on the current sense signal or the error amp

signal.

Ground planes for the low power circuitry and high power circuitry should be kept separate.

The connection

between the bottom of the current sense resistor, VSS pin and the high power ground are connected at this point.

This is a critical path and high currents should not be flowing between the current sense and VSS. Inductance in this

path should be kept to a minimum. An RC filter (shown in 2 places) will filter out the current spikes and keep the

detected noise for those circuits down to a minimum.

In the system shown, two types of current limit are implemented. The first limit is a PWM pulse by pulse limit

controlled by the motor controller. A second absolute maximum limit is set up for the MSK 4422 which will com-

pletely shut off the bridge in the event that current limit is exceeded.

When controlling the motor speed by the PWM method, it is required that the low side switches be PWM pulsed

due to the bootstrap power supplies used to power the high side switch drives. The higher the PWM speed the higher

the current load on the drive supply. PWM of the low side will prevent sagging of the high side bootstrap supplies.

The logic signals coming from the typical motor controller IC are set up for driving N channel low side and P channel

high side switches directly and are usually 15 volt levels. Provision should be made for getting 5 volt logic signals to

the MSK 4422 of the correct assertion levels. Typically, the low side signals out of the controller are high active and

the high side are low active. Inverters are shown in the system schematic for the low side controller output.

Rev. B 4/05