SMS1242 datasheet(5/11 Pages) SUMMIT

5 / 11 page

2038 2.0 6/8/00

SMS1242

SUMMIT MICROELECTRONICS, Inc.

DEVICE OPERATION

The SMS1242 provides a precision reset function for a

microcontroller or microprocessor during power-up,

power-down and brown-out conditions. The device will

monitor two independent voltage supplies and will gener-

ate a reset condition when either supply is invalid. It is

configured with two outputs, both driven by the same

conditions. They are open drain and will track each other

but the outputs are not internally tied together.

Because RESET1# and RESET2# are essentially open

drain outputs (RESET1# has a weak internal pullup,

RESET2# does not) they can be independently driven low

by external signals. This can be very useful in a dual

processor system or in a combined processor/ASIC sys-

tem where, either for system operation or system test, the

processors or ASICs must be independently held in reset

without resetting the other portion of the system.

SUPPLY MONITOR

(Assume VSENSE > VSNS) During power-up the SMS1242

monitors the supply voltage. The RESET1# and RE-

SET2# outputs are guaranteed to be driven low once VCC

reaches 1V.

As VCC rises RESET1# and RESET2#

remain asserted until VCC reaches the VRST threshold. As

VCC passes through VRST an internal timer is started to

continue driving the outputs for an additional 150ms

(nominal).

If a power-fail or brown-out condition occurs (VCC < VRST)

RESET1# and RESET2# will be asserted.

They will

remain active so long as VCC is below VRST. Because the

internal timer will be continuously reset so long as VCC is

below VRST, a brownout condition that interrupts a previ-

ously initiated reset pulse causes an additional reset delay

from the time the VCC passes back through VRST.

During power down conditions, once VCC drops below

VRST, RESET1# and RESET2# are guaranteed to be

asserted for VCC

≥ 1V.

VSENSE MONITOR

(Assume VCC is >VRST) The SMS1242 continuously

monitors the VSENSE input. The RESET1# and RE-

SET2# outputs will be driven low so long as VSENSE is <

VSNS. As VSENSE passes through VSNS an internal timer

is started to continue driving the outputs for an additional

150ms (nom.).

If a power-fail condition occurs (VSENSE falls below VSNS)

RESET1# and RESET2# will be asserted. They will re-

main active so long as VSENSE is below VSNS. Because

the internal timer will be continuously reset so long as

VSENSE is below VSNS, a brownout condition that inter-

rupts a previously initiated reset pulse causes an addi-

tional reset delay from the time VSENSE becomes greater

than VSNS.

MANUAL RESET

The manual reset input allows RESET1# and RESET2# to

be activated by a pushbutton switch.

The switch is

effectively debounced by the 100ms minimum tRST (RE-

SET pulse width). MR# can also be driven by an external

logic input that meets the 50ns minimum pulse width

required.

MCU #1

ASIC or MCU #2

RESET2#

RESET1#

VCC

Unregulated

+12V DC

DC to DC

Converter

3.3V Out

VSENSE

MR#

Test Point #1

Test Point #2

SMS1242

2038 ILL7.0

MCU

Low Voltage

High Speed

ASIC

RESET2#

RESET1#

VCC

3.3V

VSENSE

MR#

SMS1242

1.8V

2038 ILL8.0

Figure 5. Typical Multi-MCU Implementation

Figure 6. Typical Dual Voltage Implementation

SMS1242 Datasheet(PDF) 5 Page - Summit Microelectronics, Inc.

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