Compound Gate Drivers

The LM5025B contains two unique compound gate drivers,

which parallel both MOS and Bipolar devices to provide high

drive current throughout the entire switching event. The Bi-

polar device provides most of the drive current capability and

provides a relatively constant sink current which is ideal for

driving large power MOSFETs. As the switching event nears

conclusion and the Bipolar device saturates, the internal

MOS device continues to provide a low impedance to com-

pete the switching event.

During turn-off at the Miller plateau region, typically around

2V - 3V, is where gate driver current capability is needed

most. The resistive characteristics of all MOS gate drivers

are adequate for turn-on since the supply to output voltage

differential is fairly large at the Miller region. During turn-off

however, the voltage differential is small and the current

source characteristic of the Bipolar gate driver is beneficial to

provide fast drive capability.

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PWM Comparator

The PWM comparator compares the ramp signal (RAMP) to

the loop error signal (COMP). This comparator is optimized

for speed in order to achieve minimum controllable duty

cycles. The COMP pin is a high impedance comparator

input. If the opto coupler is connected between the COMP

pin and ground, then a pull-up resistor must be added be-

tween COMP and REF to bias the opto coupler transistor.

The comparator polarity is such that 0V on the COMP pin will

produce a zero duty cycle on both gate driver outputs.

Volt x Second Clamp

The Volt x Second Clamp comparator compares the ramp

signal (RAMP) to a fixed 2.5V reference. By proper selection

of RFF and CFF, the maximum ON time of the main switch

can be set to the desired duration. The ON time set by Volt

x Second Clamp varies inversely with the line voltage be-

cause the RAMP capacitor is charged by a resistor con-

nected to Vin while the threshold of the clamp is a fixed

voltage (2.5V). An example will illustrate the use of the Volt x

Second Clamp comparator to achieve a 50% duty cycle limit,

at 200KHz, at a 48V line input: A 50% duty cycle at a 200KHz

requires a 2.5µs of ON time. At 48V input the Volt x Second

product is 120V-µs (48V x 2.5µs). To achieve this clamp level

choose RFF and CFF using the following equation:.

R

48V x 2.5µs / 2.5V = 48µs

Select C

R

Ω

The recommended capacitor value range for CFF is 100pF

to 1000pF.

The C

every cycle by an internal discharge switch controlled by

either the internal clock or by the Volt x Second Clamp

comparator, whichever event occurs first.

Maximum Duty Cycle

At low line input voltages, the Volt x Second clamp will not

limit the maximum PWM duty cycle because the RAMP

signal does not charge to the 2.5V threshold voltage within

the period of the PWM clock. In this case, the maximum duty

cycle is determined by the internal PWM clock and the

output overlap or deadtime programmed by the resistor

RSET connected to the TIME pin. Referring to Figure 1, the

initial transition of OUT_B corresponds to the leading edge

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FIGURE 1.

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