For tri-level sync, the horizontal sync leading edge is trig-

gered from the positive zero-crossing reference of the tri-

level sync input with a propagation delay.

The horizontal sync output has excellent jitter performance

on its leading, negative-going edge reference because it was

optimized for video systems, which are almost always

negative-edge triggered. When the horizontal sync signal is

used in a positive-edge triggered system, like FPGA PLL, the

horizontal sync signal must be inverted beforehand to pro-

duce positive-going edges with low jitter. The horizontal sync

trailing positive-going edge should never be used as the

reference/triggered edge. This is because the horizontal

sync trailing edges are reconstructed for the equalization

and serration pulses during the vertical interval.

The LMH1981 horizontal sync edge-to-edge jitter is mea-

sured using the input-referred jitter test methodology on a

real-time digital oscilloscope by triggering on the input sync

reference edge and monitoring the horizontal sync leading

edge reference with 4-sec. variable persistence. From there,

the typical edge-to-edge jitter can be measured in the time

domain.

Vertical Sync Output

The vertical sync output (pin 8) produces an active low

vertical sync logic signal. For bi-level sync, the VSOUT

leading negative-going edge is derived from the negative-

going edge of the first vertical serration pulse with a propa-

gation delay. For tri-level sync, the VSOUT leading edge is

derived from the positive zero-crossing of the first vertical

serration pulse with a propagation delay. The vertical sync

output pulse width, T

zontal periods (3H).

Burst/Back Porch Timing Output

The burst/back porch timing output (pin 13) provides an

active low logic signal, which is pulsed low for a fixed width

during the back porch interval following the horizontal sync

pulse. This timing pulse is useful for applications that require

black level clamping or DC restoring a video signal.

For composite video, the back porch leading negative-going

edge is derived from the input sync trailing positive-going

edge with a propagation delay, and the pulse width will span

the entire color burst envelope. During the vertical interval,

the back porch leading edge is aligned with the positive-

going edge of the serration pulse with a propagation delay.

For YP

pulse behaves similar to the composite input case above,

except the pulse width is shorter due to the absence of a

color burst signal. For YP

also derived from the input sync trailing negative-going edge

with a propagation delay, and the pulse width is similar to the

horizontal sync width. During the vertical interval, the back

porch leading edge is aligned with the trailing edge of the

serration pulse.

Odd/Even Field Output

The odd/even field output (pin 14) provides a special logic

signal, which facilitates identification of odd and even fields

of interlaced formats, i.e.: 480i and 1080i. For interlaced

formats, the odd/even output is logic high during an odd field

(field 1) and logic low during an even field (field 2). The

odd/even output edge transitions align with the vertical sync

leading edge to designate the start of odd and even fields.

The output is held at logic high for progressive video formats.

Video Format Output (Lines-per-Frame Data)

The video format output counts the number of horizontal

sync pulses per field and automatically doubles it (2 fields

per frame) to approximate the total number of vertical scan

lines per frame. This vertical line count data is output to

VFOUT (pin 9) as 11-bit binary bit stream, clocked out on the

11 consecutive leading edges of horizontal sync after each

vertical sync trailing edge. Because the line count is auto-

matically doubled assuming 2 interlaced fields per frame, it

must be divided by 2 to correct for progressive formats (1

field/frame). Refer to Figure 11 and Figure 12 to see the

vertical format output timing for the 1080i interlaced format

and Figure 13 for the 480p progressive format. Outside of

these active 11-bits of data, VFOUT is held at logic low.

A sample FPGA implementation to decode the lines-per-

frame binary data and resolve the video format could be as

follows. The signal from VFOUT could be fed into the serial

input (SI) of a serial-to-parallel shift register in a FPGA. The

horizontal sync signal may be used for the clock signal (CLK)

and vertical sync for the enable (EN) and/or reset (CLR)

signals. After the 11-bits are shifted into the register, the

lines-per-frame data can be processed by the FPGA and the

video format can be determined. This could be used to

enable dynamic adjustment of various video system param-

eters, such as color space or scaler conversions.

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