LTC4010 datasheet(13/20 Pages) LINEAR

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LTC4010

4010p

Cell Voltage Network Design

An external resistor network is required to provide the

average single-cell voltage to the VCELL pin of the LTC4010.

The proper circuit for multicell packs is shown in Figure 3.

The ratio of R2 to R1 should be a factor of (n – 1), where

n is the number of series cells in the battery pack. The value

of R1 should be between 1k and 100k. This range limits the

sensing error caused by VCELL leakage current and pre-

vents the ON resistance of the internal NFET between VCDIV

and GND from causing a significant error in the VCELL

voltage. The external resistor network is also used to

detect battery insertion and removal. The filter formed by

C1 and the parallel combination of R1 and R2 is recom-

mended for rejecting PWM switching noise. The value of

C1 should be chosen to yield a 1st order lowpass fre-

quency of less than 500Hz. In the case of a single cell, the

external application circuit shown in Figure 4 is recom-

mended to provide the necessary noise filtering and miss-

ing battery detection.

APPLICATIO S I FOR ATIO

best with a 1% 10k NTC thermistor with a β of 3750.

However, the LTC4010 will operate satisfactorily with

other 10k NTC thermistors having slightly different nomi-

nal exponential temperature coefficients. For these ther-

mistors, the temperature related limits given in the Electri-

cal Characteristics table may not strictly apply. The filter

formed by C1 in Figure 5 is optional but recommended for

rejecting PWM switching noise.

Figure 4. Single-Cell Monitor Network

Figure 3. Multiple Cell Voltage Divider

BAT

LTC4010

FOR TWO OR

MORE SERIES CELLS

R2 = R1(n – 1)

4010 F03

VCDIV

GND

VCELL

BAT

10k

33nF

1 CELL

4010 F04

VCDIV

VCELL

External Thermistor

The network for proper temperature sensing using a

thermistor with a negative temperature coefficient (NTC)

is shown in Figure 5. The LTC4010 is designed to work

Figure 5. External NTC Thermistor Network

VTEMP

10k NTC

68nF

4010 F05

Disabling Thermistor Functions

Temperature sensing is optional in LTC4010 applications.

For low cost systems where temperature sensing may not

be required, the VTEMP pin may simply be wired to INTVDD

through 56k to disable temperature qualification of all

charging operations. However, this practice is not recom-

mended for NiMH cells charged well above or below their

1C rate, because fast charge termination based solely on

voltage inflection may not be adequate to protect the

battery from a severe overcharge.

INTVDD Regulator Output

If BGATE is left open, the INTVDD pin of the LTC4010 can

be used as an additional source of regulated voltage in the

host system any time READY is active. Switching loads on

INTVDD may reduce the accuracy of internal analog cir-

cuits used to monitor and terminate fast charging. In

addition, DC current drawn from the INTVDD pin can

greatly increase internal power dissipation at elevated VCC

voltages. A minimum ceramic bypass capacitor of 0.1µF is

recommended.

Calculating Average Power Dissipation

The user should ensure that the maximum rated IC junc-

tion temperature is not exceeded under all operating con-

ditions. The thermal resistance of the LTC4010 package

(θJA) is 38°C/W, provided the exposed metal pad is prop-

erly soldered to the PCB. The actual thermal resistance in

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