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LTM4686BIVPBF Datasheet(PDF) 68 Page - Analog Devices

Part # LTM4686BIVPBF
Description  Ultrathin Dual 14A or Single 28A 關Module Regulator with Digital Power System Management
PDF  130 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTM4686BIVPBF Datasheet(HTML) 68 Page - Analog Devices

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Table 20. LTM4686B Channel Output Voltage Response vs Component Matrix. 7A Load-Stepping at 7A/µs. Typical Measured Values
COUTH VENDORS PART NUMBER
COUTL VENDORS
PART NUMBER
AVX
12106D107MAT2A (100μF, 6.3V, 1210 Case Size)
Panasonic POSCAP
6TPF330M9L (330μF, 6.3V, 9mΩ ESR, D3L Case Size)
Murata
GRM32ER60J107ME20L (100μF, 6.3V, 1210 Case Size) Panasonic POSCAP
6TPD470M (470μF, 6.3V, 10mΩ ESR, D4D Case Size)
Taiyo Yuden
JMK325BJ107MM-T (100μF, 6.3V, 1210 Case Size) Panasonic POSCAP
2R5TPE470M9** (470μF, 2.5V, 9mΩ ESR, D2E Case Size)
TDK
C3225X5R0J107MT (100μF, 6.3V, 1210 Case Size) Panasonic POSCAP
6TPF470MAH (470μF, 6.3V, 10mΩ ESR, D4 Case Size)
VOUTn
(V)
VINn
(V)
REF.
CIRCUIT*
COUTHn
CERAMIC
OUTPUT
CAP
(μF)
COUTLn
BULK
OUTPUT
CAP
(μF)
CONNECT
COMPna TO
COMPnb?
(INTERNAL LOOP
COMP)
RTHn
(EXT
LOOP
COMP)
(kΩ)
CTHn
(EXT
LOOP
COMP)
(nF)
fSW
(kHz)
FSWPHCFG
PIN-
STRAP,
RESISTOR
TO SGND
(TABLE 4)
(kΩ)
VOUTn CFG
PIN-
STRAP
RESISTOR
TO SGND
(TABLE 2)
(kΩ)
VTRIMnCFG
PIN-
STRAP,
RESISTOR
TO SGND
(TABLE 3)
(kΩ)
TRANS-
IENT
DROOP
(0A
TO 7A)
(mV)
PK-PK
DEVI-
ATION
(0A
TO 7A
TO 0A)
(mV)
RECOV-
ERY
TIME
(µs)
0.9
5
Test Ckt. 1
100 ×4
None
Yes, cf. Figure 62
N/A
N/A
650
12.7
1.65
None
36
75
80
0.9
5
Test Ckt. 1
100 ×3
470
Yes, cf. Figure 62
N/A
N/A
650
12.7
1.65
None
35
70
45
1
5
Test Ckt. 1
100 ×4
None
Yes, cf. Figure 62
N/A
N/A
750
10.7
2.43
0
35
77
80
1
5
Test Ckt. 1
100 ×3
470
Yes, cf. Figure 62
N/A
N/A
750
10.7
2.43
0
32
67
60
1.2
5
Test Ckt. 1
100 ×4
None
Yes, cf. Figure 62
N/A
N/A 1000
None
3.24
0
35
76
60
1.2
5
Test Ckt. 1
100 ×3
470
Yes, cf. Figure 62
N/A
N/A 1000
None
3.24
0
31
68
60
1.5
5
Test Ckt. 1
100 ×4
None
Yes, cf. Figure 62
N/A
N/A 1000
None
4.22
None
36
74
60
1.5
5
Test Ckt. 1
100 ×3
470
Yes, cf. Figure 62
N/A
N/A 1000
None
4.22
None
31
67
60
1.8
5
Test Ckt. 1
100 ×4
None
Yes, cf. Figure 62
N/A
N/A 1000
None
6.34
0
37
79
60
1.8
5
Test Ckt. 1
100 ×3
470
Yes, cf. Figure 62
N/A
N/A 1000
None
6.34
0
31
68
60
2.5
5
Test Ckt. 1
100 ×4
None
Yes, cf. Figure 62
N/A
N/A 1000
None
10.7
None
34
77
70
2.5
5
Test Ckt. 1
100 ×3
470
Yes, cf. Figure 62
N/A
N/A 1000
None
10.7
None
29
68
70
3.3
5
Test Ckt. 1
100 ×4
None
Yes, cf. Figure 62
N/A
N/A 1000
None
22.6
None
79
170
70
3.3
5
Test Ckt. 1
100 ×3
470
Yes, cf. Figure 62
N/A
N/A 1000
None
22.6
None
64
135
70
*For all conditions: CINH input capacitance is 10µF × 2, per channel (VIN0, VIN1). CINL bulk input capacitance of 150µF is optional if VIN has very low input
impedance.
**2.5V-rated output capacitor is suitable for output voltages up to 1.8V.
LTM4686B
68
Rev. 0
For more information www.analog.com
APPLICATIONS INFORMATION



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