Preliminary Technical Data

ADL5330

REV. PrK | Page 3 of 5

Table 2. Pin Function Description

Pin

Name

Description

1,6

VPS1

Positive Supply for input stage. Nominally equal to 5 V

2,5

COM1

Common for input stage

3, 4

INHI,INLO

Differential inputs

7

VREF

Voltage reference output of 1.5 volts

8

IPBS

Input bias, normally no connection. This function is subject to change. PCB

designs should include the possibility to connect a capacitor between Pin 8 and

Pin 9.

9

OPBS

Output bias, normally no connection. This function is subject to change. PCB

designs should include the possibility to connect a capacitor between Pin 8 and

Pin 9.

10,11,12,14,

17

COM2

Common for output stage

13,18,19,20,

21,22

VPS2

Positive Supply for output stage. Nominally equal to 5 V

15

OPLO

16

OPHI

23

ENBL

Device enable, apply logic high for normal operation. Enable Threshold = 1.6 V

24

GAIN

Gain-control voltage input. Nominal Range 0 to 1.4 V.

VPS1

COM1

INLO

INHI

COM1

VPS1

GAIN

VREF

VPS2

VPS2

COM2

COM2

OPLO

OPHI

VPS2

COM2

ADL5330

T2

R2

0

C1

100 pF

C2

0.1 uF

R5

0

C7

100 pF

C8

0.1 uF

C5

100 pF

C6

100 pF

R4

0

C4

100 pF

C3

0.1 uF

C11

100 pF

C12 100 pF

R12

0

C13

100 pF

C14

0.1 uF

L2

120 nH

L1

120 nH

R6

0

C9

0.1 uF

C10

100 pF

VPOS

VPOS

VPOS

J3

Input

VPOS

VPOS

R8

0

R7

0

R9

0

R10

1nF

R11

1nF

J4

VREF

J5

IPBS

J6

OPBS

J7

Output

VPOS

SW1

R1

0

R3

0

J2

Gain

J1

Enable

VP

GND

R13

10k

R14

open

T1

50 ohm microstrip

25 ohm microstrip

25 ohm microstrip

(both sides of caps)

R15

open

50 ohm microstrip

Figure 2. ADL5330 Evaluation Board Schematic