HV2601/HV2701

DS20005391E-page 10

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Note 1: The 16 switches operate independently.

2: Serial data is clocked in on the L to H transition of the CLK.

3: All 16 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low, the

shift registers data flow through the latch.

5: Shift registers clocking has no effect on the switch states if LE is high.

6: The CLR clear input overrides all other inputs.

FIGURE 3-2:

Logic Timing Waveforms.

TABLE 3-1:

LOGIC FUNCTION TABLE

D0

D1

...

D7

D8

...

D15

LE

CLR

SW0

SW1

...

SW7

SW8

...

SW15

L—

...

——

...

—L

L

OFF

—

...

——

...

—

H

—

——

—

L

L

ON

—

——

—

—L

—

—

—L

L—

OFF

—

—

—

—

H

——

—

L

L

—

ON

——

—

—

—

—

—

—

L

L

—

——

——

—

—

—

—

—

L

L

—

——

——

——

L

—

—

L

L

—

—

OFF

—

—

——

H

—

—

L

L

—

—

ON

—

—

—

—

—L

—L

L—

—

—

OFF

—

——

—

H

—

L

L

—

—

—

ON

—

—

—

—

—

—

L

L

—

——

——

—

—

—

—

—

L

L

—

——

——

—

—

—

—

—

L

L

—

——

——

—

—

—

—

—

L

L

—

——

——

——

—

—

L

L

L

—

—

—

—

OFF

——

—

—

H

L

L

—

—

—

—

ON

X

X

X

X

X

X

X

H

L

HOLD PREVIOUS STATE

X

X

X

X

X

X

X

X

H

ALL SWITCHES OFF

DATA IN

DIN

LE

CLOCK

CLK

DATA OUT

DOUT

OFF

V

OUT

(typ)

ON

CLR

50%

50%

50%

50%

t

WLE

t

SD

t

SU

t

h

50%

50%

t

OFF

50%

t

DO

DO

t

ON

t

WCL

D

N+1

D

N

D

N-1

50%

50%

90%

10%