MCP6V5XTESLASHMS datasheet(22/50 Pages) MICROCHIP

22 / 50 page

MCP6V51/2/4

DS20006136B-page 22

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4.2

Other Functional Blocks

4.2.1

INPUT PROTECTION

The MCP6V5X op amps can be operated on a single

supply, voltage ranging from 4.5V to 45V, or in a split-

supply application (±2.25V to ±22.5V). The input

Common-Mode range extends below the negative rail,

VCML = VSS – 0.3V at +25°C, while maintaining high

CMRR (135 dB min. at 45 VDD). The upper range of the

input Common-Mode is limited to VCMH = VDD – 2.1V.

To ensure proper operation, these VCM limits, along

with any potential overvoltage/current conditions as

described in the following paragraphs, should be taken

into consideration.

4.2.1.1

Phase Reversal

The input circuitry of the MCP6V5X amplifiers is

designed to not exhibit phase reversal when the input

pins (VIN+, VIN-) exceed the supply voltages. Typically,

an amplifier is most susceptible to phase reversal when

operated in a unity gain buffer configuration, where the

input is prone to be driven beyond the specified

Common-Mode voltage range.

FIGURE 4-4:

No Phase Reversal.

Figure 4-4 shows an input voltage exceeding the supply

voltages by 0.5V for each rail. The output voltage

remains railed with no phase inversion while the input

is overdriven. For this particular example, the supply

voltage was kept lower in order to help visualize the

relationship between the input and output voltages

during an Overvoltage condition.

4.2.1.2

Input Voltage Limits

In order to prevent damage and/or improper operation

of these amplifiers, the surrounding circuit must limit

the voltage levels seen by the amplifier’s input pins to

within the specified limits (see

Section 1.1 “Absolute

Maximum Ratings†”). This input voltage limit

requirement is independent of the current limits

discussed later on.

Figure 4-5 illustrates the principle ESD protection

scheme used for the MCP6V5X amplifiers. Each input

is protected by a set of primary and secondary steering

diodes in addition to series resistance. Furthermore, a

set of anti-parallel diodes protect the input transistors

from seeing a large differential voltage. This structure

was chosen to protect the input transistors against

many (but not all) ESD and Overvoltage conditions,

while also minimizing the effects of additional input bias

currents (IBias) resulting from the leakage current of the

ESD devices. Note that this leakage current is

temperature-dependent and will dominate at higher

temperatures (see Figure 2-15).

FIGURE 4-5:

Simplified Analog Input ESD

Structures.

The input ESD diodes clamp the inputs when they try

to go more than one diode drop below VSS. They also

clamp any voltages well above VDD; their breakdown

voltage is high enough to allow normal operation, but

not low enough to protect against slow overvoltage

(beyond VDD) events. Very fast ESD events (that meet

the specification) are limited so that damage can

largely be prevented. The internal ESD protection

scheme is intended to protect the device during test,

assembly and manufacturing process. Note that the

internal protection is not intended to be used as

clamping or limiting devices for sustained in-circuit

operation. If such Overvoltage (i.e., exceeding the

supply rails by more than 0.5V) and/or Overcurrent

conditions (i.e., current flow at each input pin

exceeding 5 mA) are expected as part of the

application circuit, external protection devices may be

needed.

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