18

PowerPC 604e RISC Microprocessor Technical Summary

Figure 5. PowerPC 604e Microprocessor Signal Groups

1.2.12 Clocking

The 604e has a phase-locked loop (PLL) that generates the internal processor clock. The input, or reference

signal, to the PLL is the bus clock. The feedback in the PLL guarantees that the processor clock is phase

locked to the bus clock, regardless of process variations, temperature changes, or parasitic capacitances. The

PLL also ensures a 50% duty cycle for the processor clock.

BUS REQUEST

BUS GRANT

ADDRESS BUS BUSY

TRANSFER START

EXTENDED TRANSFER START

ADDRESS

ADDRESS PARITY

ADDRESS PARITY ERROR

TRANSFER TYPE

TRANSFER CODE

TRANSFER SIZE

TRANSFER BURST

CACHE INHIBIT

WRITE THROUGH

GLOBAL

ADDRESS ACKNOWLEDGE

CACHE SET MEMBER

ADDRESS RETRY

SHARED

DATA

ARBITRATION

ADDRESS

START

ADDRESS

TRANSFER

TRANSFER

ATTRIBUTE

ADDRESS

TERMINATION

DATA BUS GRANT

DATA BUS WRITE ONLY

DATA BUS BUSY

DATA

DATA PARITY

DATA PARITY ERROR

TRANSFER ACKNOWLEDGE

DATA RETRY

TRANSFER ERROR ACK

INTERRUPT

SYSTEM RESET

1

1

1

1

1

32

4

1

5

3

3

1

1

1

1

2

1

1

1

1

1

1

64

8

1

1

1

1

1

1

1

ADDRESS

ARBITRATION

DATA

TRANSFER

DATA

TERMINATION

INTERRUPT

TEST ACCESS PORT

JTAG / COP

1

1

SYSTEM CLOCK

1

TOTAL: 171

CHECKSTOP INPUT_

1

STATE

PROCESSOR

CHECKSTOP_OUTPUT_

RESERVATION

TEST DATA OUT

4

CLOCK

ENABLE TIMEBASE

1

MACHINE CHECK_

1

DATA BUS DISABLE

1

1

HARD RESET

DRIVER MODE

2

MISC

L2_INT

1

RUN

1

HALTED

1

SYSTEM MANAGEMENT

1

PLL CONFIG

4

CLOCK OUT

1

1

ANALOG VDD

SIGNALS